// Generator : SpinalHDL v1.10.1    git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
// Component : CPUSimple

`timescale 1ns/1ps

module CPUSimple (
  output wire          icache_cmd_valid,
  input  wire          icache_cmd_ready,
  output wire [31:0]   icache_cmd_payload_addr,
  input  wire          icache_rsp_valid,
  input  wire [31:0]   icache_rsp_payload_data,
  output wire          dcache_cmd_valid,
  input  wire          dcache_cmd_ready,
  output wire [31:0]   dcache_cmd_payload_addr,
  output wire          dcache_cmd_payload_wen,
  output wire [31:0]   dcache_cmd_payload_wdata,
  output wire [3:0]    dcache_cmd_payload_wstrb,
  output wire [1:0]    dcache_cmd_payload_size,
  input  wire          dcache_rsp_valid,
  input  wire [31:0]   dcache_rsp_payload_data,
  input  wire          clk,
  input  wire          reset
);
  localparam AluCtrlEnum_ADD = 5'd0;
  localparam AluCtrlEnum_SUB = 5'd1;
  localparam AluCtrlEnum_SLT = 5'd2;
  localparam AluCtrlEnum_SLTU = 5'd3;
  localparam AluCtrlEnum_NOR_1 = 5'd4;
  localparam AluCtrlEnum_XOR_1 = 5'd5;
  localparam AluCtrlEnum_SLL_1 = 5'd6;
  localparam AluCtrlEnum_SRL_1 = 5'd7;
  localparam AluCtrlEnum_SRA_1 = 5'd8;
  localparam AluCtrlEnum_AND_1 = 5'd9;
  localparam AluCtrlEnum_OR_1 = 5'd10;
  localparam AluCtrlEnum_LUI = 5'd11;
  localparam AluCtrlEnum_JIRL = 5'd12;
  localparam AluCtrlEnum_BEQ = 5'd13;
  localparam AluCtrlEnum_BNE = 5'd14;
  localparam AluCtrlEnum_BLT = 5'd15;
  localparam AluCtrlEnum_BGE = 5'd16;
  localparam AluCtrlEnum_BLTU = 5'd17;
  localparam AluCtrlEnum_BGEU = 5'd18;
  localparam AluCtrlEnum_CSR = 5'd19;
  localparam AluCtrlEnum_MUL = 5'd20;
  localparam AluCtrlEnum_MULH = 5'd21;
  localparam AluCtrlEnum_MULHU = 5'd22;
  localparam AluCtrlEnum_DIV = 5'd23;
  localparam AluCtrlEnum_DIVU = 5'd24;
  localparam AluCtrlEnum_BL = 5'd25;
  localparam MemCtrlEnum_IDLE = 4'd0;
  localparam MemCtrlEnum_LD_B = 4'd1;
  localparam MemCtrlEnum_LD_H = 4'd2;
  localparam MemCtrlEnum_LD_W = 4'd3;
  localparam MemCtrlEnum_LD_BU = 4'd4;
  localparam MemCtrlEnum_LD_HU = 4'd5;
  localparam MemCtrlEnum_ST_B = 4'd6;
  localparam MemCtrlEnum_ST_H = 4'd7;
  localparam MemCtrlEnum_ST_W = 4'd8;
  localparam MemCtrlEnum_LL = 4'd9;
  localparam MemCtrlEnum_SC = 4'd10;
  localparam CsrCtrlEnum_CSRRD = 4'd0;
  localparam CsrCtrlEnum_CSRWR = 4'd1;
  localparam CsrCtrlEnum_CSRXCHG = 4'd2;
  localparam CsrCtrlEnum_SYSCALL = 4'd3;
  localparam CsrCtrlEnum_ERTN = 4'd4;
  localparam CsrCtrlEnum_BREAK_1 = 4'd5;
  localparam CsrCtrlEnum_ADEF = 4'd6;
  localparam CsrCtrlEnum_ALE = 4'd7;
  localparam CsrCtrlEnum_INE = 4'd8;

  wire                regFileModule_1_write_ports_rd_wen;
  wire       [13:0]   csrRegfile_1_cpu_ports_waddr;
  wire       [13:0]   csrRegfile_1_cpu_ports_raddr;
  wire       [31:0]   csrRegfile_1_cpu_ports_pc;
  wire                fetch_FetchPlugin_pc_stream_fifo_ports_m_ports_valid;
  wire       [31:0]   fetch_FetchPlugin_pc_stream_fifo_ports_m_ports_payload;
  wire                fetch_FetchPlugin_pc_stream_fifo_ports_s_ports_ready;
  wire       [31:0]   fetch_FetchPlugin_pc_stream_fifo_next_payload;
  wire                fetch_FetchPlugin_pc_stream_fifo_next_valid;
  wire                fetch_FetchPlugin_predict_taken_fifo_ports_m_ports_valid;
  wire                fetch_FetchPlugin_predict_taken_fifo_ports_m_ports_payload;
  wire                fetch_FetchPlugin_predict_taken_fifo_ports_s_ports_ready;
  wire                fetch_FetchPlugin_instruction_stream_fifo_ports_m_ports_valid;
  wire       [31:0]   fetch_FetchPlugin_instruction_stream_fifo_ports_m_ports_payload;
  wire                fetch_FetchPlugin_instruction_stream_fifo_ports_s_ports_ready;
  wire       [31:0]   regFileModule_1_read_ports_rs1_value;
  wire       [31:0]   regFileModule_1_read_ports_rs2_value;
  wire                gshare_predictor_1_predict_taken;
  wire       [6:0]    gshare_predictor_1_predict_history;
  wire       [31:0]   gshare_predictor_1_predict_pc_next;
  wire       [31:0]   csrRegfile_1_cpu_ports_rdata;
  wire                csrRegfile_1_cpu_ports_wvalid;
  wire                csrRegfile_1_cpu_ports_int_pc;
  wire       [31:0]   csrRegfile_1_cpu_ports_pc_next;
  wire                lLbitModule_1_read_ports_LLbit_data;
  wire       [31:0]   tmp_pc_next_1;
  wire       [31:0]   tmp_decode_DecodePlugin_is_adef;
  wire       [31:0]   tmp_tmp_decode_DecodePlugin_imm_8;
  wire       [31:0]   tmp_tmp_decode_DecodePlugin_imm_8_1;
  wire       [31:0]   tmp_tmp_decode_DecodePlugin_imm_8_2;
  wire       [31:0]   tmp_tmp_decode_RS1;
  wire       [31:0]   tmp_tmp_decode_RS1_1;
  wire       [31:0]   tmp_tmp_decode_RS1_2;
  wire       [31:0]   tmp_decode_DecodePlugin_rs1_eq_rs2;
  wire       [31:0]   tmp_decode_DecodePlugin_rs1_eq_rs2_1;
  wire       [31:0]   tmp_decode_DecodePlugin_rs1_ne_rs2;
  wire       [31:0]   tmp_decode_DecodePlugin_rs1_ne_rs2_1;
  wire       [31:0]   tmp_decode_DecodePlugin_rs1_lt_rs2;
  wire       [31:0]   tmp_decode_DecodePlugin_rs1_lt_rs2_1;
  wire       [31:0]   tmp_decode_DecodePlugin_rs1_ge_rs2;
  wire       [31:0]   tmp_decode_DecodePlugin_rs1_ge_rs2_1;
  wire       [31:0]   tmp_tmp_decode_DecodePlugin_link_addr;
  wire       [31:0]   tmp_tmp_decode_DecodePlugin_link_addr_1;
  wire       [31:0]   tmp_tmp_decode_DecodePlugin_link_addr_2;
  wire       [31:0]   tmp_tmp_decode_DecodePlugin_link_addr_3;
  wire       [31:0]   tmp_tmp_decode_DecodePlugin_pc_next;
  wire       [31:0]   tmp_tmp_decode_DecodePlugin_pc_next_1;
  wire       [31:0]   tmp_tmp_decode_DecodePlugin_pc_next_2;
  wire       [31:0]   tmp_tmp_decode_DecodePlugin_pc_next_3;
  wire       [31:0]   tmp_tmp_decode_DecodePlugin_pc_next_4;
  wire       [31:0]   tmp_tmp_decode_DecodePlugin_pc_next_5;
  wire                tmp_when;
  wire                tmp_when_1;
  wire                tmp_when_2;
  wire                tmp_when_3;
  wire                tmp_when_4;
  wire       [4:0]    tmp_8;
  wire       [4:0]    tmp_9;
  wire       [31:0]   tmp_execute_AluPlugin_sub_result;
  wire       [31:0]   tmp_execute_AluPlugin_sub_result_1;
  wire       [31:0]   tmp_execute_AluPlugin_sra_result;
  wire       [31:0]   tmp_execute_AluPlugin_add_result;
  wire       [31:0]   tmp_execute_AluPlugin_add_result_1;
  wire       [31:0]   tmp_execute_AluPlugin_slt_result;
  wire       [31:0]   tmp_execute_AluPlugin_slt_result_1;
  wire       [4:0]    tmp_memaccess_LsuPlugin_dcache_rdata;
  wire                tmp_when_5;
  wire       [31:0]   tmp_tmp_memaccess_LsuPlugin_is_ale;
  wire       [31:0]   tmp_tmp_memaccess_LsuPlugin_is_ale_1;
  wire       [31:0]   tmp_tmp_memaccess_LsuPlugin_is_ale_2;
  wire       [31:0]   tmp_tmp_memaccess_LsuPlugin_is_ale_3;
  wire       [31:0]   tmp_tmp_memaccess_LsuPlugin_is_ale_4;
  wire       [31:0]   tmp_tmp_memaccess_LsuPlugin_is_ale_5;
  wire       [31:0]   tmp_tmp_memaccess_LsuPlugin_is_ale_6;
  wire       [4:0]    tmp_memaccess_LsuPlugin_lsu_wdata;
  wire       [31:0]   writeback_RD;
  wire       [31:0]   memaccess_RD;
  wire                memaccess_LSU_HOLD;
  wire                memaccess_LLBIT_DATA;
  wire                memaccess_LLBIT_WE;
  wire                memaccess_IS_ALE;
  wire       [31:0]   execute_ALU_RESULT;
  wire       [31:0]   decode_CSR_RDATA;
  wire       [14:0]   decode_CSR_CODE;
  wire                execute_IS_CSR;
  wire                decode_IS_CSR;
  wire                decode_CSR_WEN;
  wire       [3:0]    decode_CSR_CTRL;
  wire       [31:0]   execute_MEM_WDATA;
  wire       [31:0]   decode_MEM_WDATA;
  wire                execute_IS_STORE;
  wire                decode_IS_STORE;
  wire                decode_IS_LOAD;
  wire       [3:0]    execute_MEM_CTRL;
  wire       [3:0]    decode_MEM_CTRL;
  wire       [6:0]    decode_BRANCH_HISTORY;
  wire                decode_IS_RETURN;
  wire                decode_IS_JUMP;
  wire                decode_IS_CALL;
  wire       [31:0]   execute_REDIRECT_PC_NEXT;
  wire       [31:0]   decode_REDIRECT_PC_NEXT;
  wire                execute_REDIRECT_VALID;
  wire                decode_REDIRECT_VALID;
  wire       [31:0]   decode_LINK_ADDR;
  wire                decode_BRANCH_TAKEN;
  wire                decode_BRANCH_OR_JUMP;
  wire       [4:0]    writeback_RD_ADDR;
  wire       [4:0]    memaccess_RD_ADDR;
  wire       [4:0]    execute_RD_ADDR;
  wire       [4:0]    decode_RD_ADDR;
  wire                writeback_RD_WEN;
  wire                memaccess_RD_WEN;
  wire                execute_RD_WEN;
  wire                decode_RD_WEN;
  wire       [4:0]    decode_ALU_CTRL;
  wire                execute_INT_PC;
  wire                decode_INT_PC;
  wire       [31:0]   fetch_PREDICT_PC;
  wire                fetch_PREDICT_TAKEN;
  wire                fetch_PREDICT_VALID;
  wire       [31:0]   memaccess_INSTRUCTION;
  wire       [31:0]   execute_INSTRUCTION;
  wire       [31:0]   fetch_INSTRUCTION;
  wire       [31:0]   fetch_PC_NEXT;
  wire       [31:0]   memaccess_PC;
  wire       [31:0]   fetch_PC;
  wire       [31:0]   writeback_INSTRUCTION;
  wire       [31:0]   writeback_PC;
  wire                writeback_LLBIT_WE;
  wire                writeback_LLBIT_DATA;
  wire       [31:0]   memaccess_CSR_RDATA;
  wire                memaccess_IS_CSR;
  wire       [31:0]   memaccess_LSU_RDATA;
  wire       [3:0]    memaccess_MEM_CTRL;
  wire                memaccess_LLBIT;
  wire       [31:0]   memaccess_MEM_WDATA;
  wire                memaccess_IS_LOAD;
  reg                 memaccess_IS_STORE;
  wire       [31:0]   memaccess_ALU_RESULT;
  wire                execute_CSR_WEN;
  wire       [31:0]   execute_PC;
  wire       [13:0]   execute_CSR_ADDR;
  wire       [14:0]   execute_CSR_CODE;
  wire       [3:0]    execute_CSR_CTRL;
  wire       [31:0]   execute_CSR_RDATA;
  wire       [13:0]   decode_CSR_ADDR;
  wire                tmp_memaccess_arbitration_haltItself;
  wire                execute_IS_LOAD;
  wire                tmp_fetch_arbitration_flushIt;
  wire                tmp_fetch_arbitration_flushIt_1;
  wire       [4:0]    tmp_DecodePlugin_hazard_rs1_from_ex;
  wire                tmp_DecodePlugin_hazard_rs1_from_ex_1;
  wire                decode_RS2_REQ;
  wire       [4:0]    decode_RS2_ADDR;
  wire                decode_RS1_REQ;
  wire       [4:0]    decode_RS1_ADDR;
  wire       [4:0]    tmp_DecodePlugin_hazard_rs1_from_mem;
  wire                tmp_DecodePlugin_hazard_rs1_from_mem_1;
  wire       [31:0]   execute_LINK_ADDR;
  wire       [4:0]    execute_ALU_CTRL;
  wire       [31:0]   execute_RS2;
  wire       [31:0]   execute_RS1;
  wire       [31:0]   tmp_decode_to_execute_REDIRECT_PC_NEXT;
  wire       [31:0]   tmp_decode_to_execute_PC;
  wire                tmp_fetch_arbitration_flushIt_2;
  wire       [31:0]   decode_PC_NEXT;
  wire                decode_PREDICT_TAKEN;
  wire       [31:0]   decode_RS2;
  wire       [31:0]   decode_RS1;
  wire                decode_RS2_FROM_MEM;
  reg        [31:0]   tmp_decode_RS2;
  wire                decode_RS2_FROM_EX;
  wire       [31:0]   tmp_memaccess_to_writeback_RD;
  wire                decode_RS1_FROM_MEM;
  wire       [31:0]   tmp_execute_to_memaccess_ALU_RESULT;
  reg        [31:0]   tmp_decode_RS1;
  wire                decode_RS1_FROM_EX;
  wire       [31:0]   decode_INSTRUCTION;
  wire       [31:0]   decode_PC;
  wire       [31:0]   fetch_BPU_PC_NEXT;
  wire       [31:0]   fetch_CSR_PC;
  wire                fetch_INT_PC;
  wire                tmp_pc_next;
  wire                fetch_BPU_BRANCH_TAKEN;
  wire                fetch_arbitration_haltItself;
  wire                fetch_arbitration_haltByOther;
  reg                 fetch_arbitration_removeIt;
  wire                fetch_arbitration_flushIt;
  wire                fetch_arbitration_flushNext;
  wire                fetch_arbitration_isValid;
  wire                fetch_arbitration_isStuck;
  wire                fetch_arbitration_isStuckByOthers;
  wire                fetch_arbitration_isFlushed;
  wire                fetch_arbitration_isMoving;
  wire                fetch_arbitration_isFiring;
  wire                decode_arbitration_haltItself;
  wire                decode_arbitration_haltByOther;
  reg                 decode_arbitration_removeIt;
  wire                decode_arbitration_flushIt;
  wire                decode_arbitration_flushNext;
  reg                 decode_arbitration_isValid;
  wire                decode_arbitration_isStuck;
  wire                decode_arbitration_isStuckByOthers;
  wire                decode_arbitration_isFlushed;
  wire                decode_arbitration_isMoving;
  wire                decode_arbitration_isFiring;
  wire                execute_arbitration_haltItself;
  wire                execute_arbitration_haltByOther;
  reg                 execute_arbitration_removeIt;
  wire                execute_arbitration_flushIt;
  wire                execute_arbitration_flushNext;
  reg                 execute_arbitration_isValid;
  wire                execute_arbitration_isStuck;
  wire                execute_arbitration_isStuckByOthers;
  wire                execute_arbitration_isFlushed;
  wire                execute_arbitration_isMoving;
  wire                execute_arbitration_isFiring;
  wire                memaccess_arbitration_haltItself;
  wire                memaccess_arbitration_haltByOther;
  reg                 memaccess_arbitration_removeIt;
  wire                memaccess_arbitration_flushIt;
  wire                memaccess_arbitration_flushNext;
  reg                 memaccess_arbitration_isValid;
  wire                memaccess_arbitration_isStuck;
  wire                memaccess_arbitration_isStuckByOthers;
  wire                memaccess_arbitration_isFlushed;
  wire                memaccess_arbitration_isMoving;
  wire                memaccess_arbitration_isFiring;
  wire                writeback_arbitration_haltItself;
  wire                writeback_arbitration_haltByOther;
  reg                 writeback_arbitration_removeIt;
  wire                writeback_arbitration_flushIt;
  wire                writeback_arbitration_flushNext;
  reg                 writeback_arbitration_isValid;
  wire                writeback_arbitration_isStuck;
  wire                writeback_arbitration_isStuckByOthers;
  wire                writeback_arbitration_isFlushed;
  wire                writeback_arbitration_isMoving;
  wire                writeback_arbitration_isFiring;
  wire                DecodePlugin_hazard_decode_rs1_req;
  wire                DecodePlugin_hazard_decode_rs2_req;
  wire       [4:0]    DecodePlugin_hazard_decode_rs1_addr;
  wire       [4:0]    DecodePlugin_hazard_decode_rs2_addr;
  wire                DecodePlugin_hazard_rs1_from_mem;
  wire                DecodePlugin_hazard_rs2_from_mem;
  wire                DecodePlugin_hazard_rs1_from_ex;
  wire                DecodePlugin_hazard_rs2_from_ex;
  wire                DecodePlugin_hazard_rs1_load_hit;
  wire                DecodePlugin_hazard_rs2_load_hit;
  wire                DecodePlugin_hazard_ctrl_load_use;
  wire                ICachePlugin_icache_access_cmd_valid;
  wire                ICachePlugin_icache_access_cmd_ready;
  wire       [31:0]   ICachePlugin_icache_access_cmd_payload_addr;
  wire                ICachePlugin_icache_access_rsp_valid;
  wire       [31:0]   ICachePlugin_icache_access_rsp_payload_data;
  wire                DCachePlugin_dcache_access_cmd_valid;
  wire                DCachePlugin_dcache_access_cmd_ready;
  wire       [31:0]   DCachePlugin_dcache_access_cmd_payload_addr;
  wire                DCachePlugin_dcache_access_cmd_payload_wen;
  wire       [31:0]   DCachePlugin_dcache_access_cmd_payload_wdata;
  wire       [3:0]    DCachePlugin_dcache_access_cmd_payload_wstrb;
  wire       [1:0]    DCachePlugin_dcache_access_cmd_payload_size;
  wire                DCachePlugin_dcache_access_rsp_valid;
  wire       [31:0]   DCachePlugin_dcache_access_rsp_payload_data;
  wire                DCachePlugin_dcache_access_stall;
  reg        [31:0]   pc_next;
  reg                 fetch_valid;
  reg                 rsp_flush;
  wire                ICachePlugin_icache_access_cmd_fire;
  wire                fetch_FetchPlugin_bpu_predict_taken;
  wire                fetch_FetchPlugin_pc_in_stream_valid;
  wire                fetch_FetchPlugin_pc_in_stream_ready;
  wire       [31:0]   fetch_FetchPlugin_pc_in_stream_payload;
  wire                fetch_FetchPlugin_pc_out_stream_valid;
  wire                fetch_FetchPlugin_pc_out_stream_ready;
  wire       [31:0]   fetch_FetchPlugin_pc_out_stream_payload;
  wire                fetch_FetchPlugin_predict_taken_in_valid;
  wire                fetch_FetchPlugin_predict_taken_in_ready;
  wire                fetch_FetchPlugin_predict_taken_in_payload;
  wire                fetch_FetchPlugin_predict_taken_out_valid;
  wire                fetch_FetchPlugin_predict_taken_out_ready;
  wire                fetch_FetchPlugin_predict_taken_out_payload;
  wire                fetch_FetchPlugin_instruction_in_stream_valid;
  wire                fetch_FetchPlugin_instruction_in_stream_ready;
  wire       [31:0]   fetch_FetchPlugin_instruction_in_stream_payload;
  wire                fetch_FetchPlugin_instruction_out_stream_valid;
  wire                fetch_FetchPlugin_instruction_out_stream_ready;
  wire       [31:0]   fetch_FetchPlugin_instruction_out_stream_payload;
  wire                fetch_FetchPlugin_fifo_all_valid;
  wire       [1:0]    IDLE;
  wire       [1:0]    FETCH;
  wire       [1:0]    HALT;
  wire       [1:0]    fetch_state_next;
  reg        [1:0]    fetch_state;
  wire                ICachePlugin_icache_access_cmd_isStall;
  reg        [1:0]    tmp_fetch_state_next;
  wire       [31:0]   decode_DecodePlugin_rs1;
  wire       [31:0]   decode_DecodePlugin_rs2;
  reg        [31:0]   decode_DecodePlugin_imm;
  wire                decode_DecodePlugin_rs1_req;
  wire                decode_DecodePlugin_rs2_req;
  wire       [4:0]    decode_DecodePlugin_rs1_addr;
  wire       [4:0]    decode_DecodePlugin_rs2_addr;
  wire       [4:0]    decode_DecodePlugin_rd_addr;
  wire                decode_DecodePlugin_rd_wen;
  wire       [4:0]    decode_DecodePlugin_alu_ctrl;
  wire       [31:0]   decode_DecodePlugin_link_addr;
  wire                decode_DecodePlugin_fetch_dec_branch;
  wire                decode_DecodePlugin_rs1_eq_rs2;
  wire                decode_DecodePlugin_rs1_ne_rs2;
  wire                decode_DecodePlugin_rs1_lt_rs2;
  wire                decode_DecodePlugin_rs1_ge_rs2;
  wire                decode_DecodePlugin_rs1_ltu_rs2;
  wire                decode_DecodePlugin_rs1_geu_rs2;
  wire       [31:0]   decode_DecodePlugin_pc_next;
  wire                decode_DecodePlugin_is_jirl;
  wire                decode_DecodePlugin_is_branch;
  reg                 decode_DecodePlugin_is_call;
  reg                 decode_DecodePlugin_is_return;
  reg                 decode_DecodePlugin_is_jump;
  wire                decode_DecodePlugin_is_bl;
  reg        [31:0]   decode_DecodePlugin_redirect_pc_next;
  reg                 decode_DecodePlugin_redirect_valid;
  reg        [6:0]    decode_DecodePlugin_branch_history;
  wire                decode_DecodePlugin_is_load;
  wire                decode_DecodePlugin_is_store;
  wire       [3:0]    decode_DecodePlugin_mem_ctrl;
  wire       [31:0]   decode_DecodePlugin_mem_wdata;
  reg        [3:0]    decode_DecodePlugin_csr_ctrl;
  wire       [13:0]   decode_DecodePlugin_csr_addr;
  wire                decode_DecodePlugin_csr_wen;
  wire                decode_DecodePlugin_is_csr;
  wire       [14:0]   decode_DecodePlugin_csr_code;
  wire                decode_DecodePlugin_is_adef;
  wire                decode_DecodePlugin_is_ine;
  reg                 tmp_1;
  reg        [19:0]   tmp_decode_DecodePlugin_imm;
  wire                tmp_decode_DecodePlugin_imm_1;
  reg        [19:0]   tmp_decode_DecodePlugin_imm_2;
  reg        [26:0]   tmp_decode_DecodePlugin_imm_3;
  wire                tmp_decode_DecodePlugin_imm_4;
  reg        [15:0]   tmp_decode_DecodePlugin_imm_5;
  wire                tmp_decode_DecodePlugin_imm_6;
  reg        [17:0]   tmp_decode_DecodePlugin_imm_7;
  reg        [31:0]   tmp_decode_DecodePlugin_imm_8;
  reg                 tmp_2;
  reg                 tmp_3;
  reg                 tmp_4;
  reg                 tmp_5;
  reg                 tmp_6;
  reg                 tmp_7;
  reg        [4:0]    tmp_decode_DecodePlugin_alu_ctrl;
  reg        [4:0]    tmp_decode_DecodePlugin_rs1_addr;
  reg                 tmp_decode_DecodePlugin_rs1_req;
  reg        [4:0]    tmp_decode_DecodePlugin_rs2_addr;
  reg                 tmp_decode_DecodePlugin_rs2_req;
  reg        [4:0]    tmp_decode_DecodePlugin_rd_addr;
  reg                 tmp_decode_DecodePlugin_rd_wen;
  reg        [31:0]   tmp_decode_DecodePlugin_link_addr;
  reg                 tmp_decode_DecodePlugin_fetch_dec_branch;
  reg        [31:0]   tmp_decode_DecodePlugin_pc_next;
  reg                 tmp_decode_DecodePlugin_is_branch;
  reg        [3:0]    tmp_decode_DecodePlugin_mem_ctrl;
  reg        [31:0]   tmp_decode_DecodePlugin_mem_wdata;
  reg                 tmp_decode_DecodePlugin_is_load;
  reg                 tmp_decode_DecodePlugin_is_store;
  reg                 tmp_decode_DecodePlugin_is_ine;
  reg        [3:0]    tmp_decode_DecodePlugin_csr_ctrl;
  reg        [3:0]    tmp_decode_DecodePlugin_csr_ctrl_1;
  reg                 tmp_decode_DecodePlugin_csr_wen;
  reg                 tmp_decode_DecodePlugin_csr_wen_1;
  reg                 tmp_decode_DecodePlugin_is_csr;
  reg        [14:0]   tmp_decode_DecodePlugin_csr_code;
  wire       [31:0]   execute_AluPlugin_src1;
  wire       [31:0]   execute_AluPlugin_src2;
  wire       [31:0]   execute_AluPlugin_sub_result;
  wire       [4:0]    execute_AluPlugin_shift_bits;
  wire       [31:0]   execute_AluPlugin_sll_result;
  wire       [31:0]   execute_AluPlugin_srl_result;
  wire       [31:0]   execute_AluPlugin_sra_result;
  wire       [31:0]   execute_AluPlugin_or_result;
  wire       [31:0]   execute_AluPlugin_and_result;
  wire       [31:0]   execute_AluPlugin_xor_result;
  wire       [31:0]   execute_AluPlugin_nor_result;
  wire       [31:0]   execute_AluPlugin_add_result;
  wire       [31:0]   execute_AluPlugin_alu_result;
  wire                execute_AluPlugin_slt_result;
  wire                execute_AluPlugin_sltu_result;
  reg        [31:0]   tmp_execute_AluPlugin_alu_result;
  wire       [31:0]   execute_ExcepPlugin_csr_wdata;
  wire       [31:0]   execute_ExcepPlugin_csrxchg_wdata;
  wire                execute_ExcepPlugin_is_ertn;
  wire                execute_ExcepPlugin_is_syscall;
  wire                execute_ExcepPlugin_is_break;
  wire                execute_ExcepPlugin_is_adef;
  wire                execute_ExcepPlugin_is_ine;
  reg        [31:0]   tmp_execute_ExcepPlugin_csr_wdata;
  wire       [31:0]   memaccess_LsuPlugin_cpu_addr;
  wire                memaccess_LsuPlugin_is_mem;
  wire       [1:0]    memaccess_LsuPlugin_cpu_addr_sel;
  wire       [31:0]   memaccess_LsuPlugin_lsu_addr;
  wire       [31:0]   memaccess_LsuPlugin_lsu_rdata;
  wire       [31:0]   memaccess_LsuPlugin_lsu_wdata;
  wire                memaccess_LsuPlugin_lsu_wen;
  wire       [3:0]    memaccess_LsuPlugin_lsu_wstrb;
  wire       [1:0]    memaccess_LsuPlugin_lsu_size;
  wire       [31:0]   memaccess_LsuPlugin_dcache_rdata;
  wire                tmp_memaccess_LsuPlugin_dcache_ld_b;
  reg        [23:0]   tmp_memaccess_LsuPlugin_dcache_ld_b_1;
  wire       [31:0]   memaccess_LsuPlugin_dcache_ld_b;
  reg        [23:0]   tmp_memaccess_LsuPlugin_dcache_ld_bu;
  wire       [31:0]   memaccess_LsuPlugin_dcache_ld_bu;
  wire                tmp_memaccess_LsuPlugin_dcache_ld_h;
  reg        [15:0]   tmp_memaccess_LsuPlugin_dcache_ld_h_1;
  wire       [31:0]   memaccess_LsuPlugin_dcache_ld_h;
  reg        [15:0]   tmp_memaccess_LsuPlugin_dcache_ld_hu;
  wire       [31:0]   memaccess_LsuPlugin_dcache_ld_hu;
  wire       [31:0]   memaccess_LsuPlugin_dcache_ld_w;
  wire       [31:0]   memaccess_LsuPlugin_dcache_data_load;
  wire                tmp_memaccess_LsuPlugin_dcache_st_b;
  reg        [23:0]   tmp_memaccess_LsuPlugin_dcache_st_b_1;
  wire       [31:0]   memaccess_LsuPlugin_dcache_st_b;
  wire                tmp_memaccess_LsuPlugin_dcache_st_h;
  reg        [15:0]   tmp_memaccess_LsuPlugin_dcache_st_h_1;
  wire       [31:0]   memaccess_LsuPlugin_dcache_st_h;
  wire       [31:0]   memaccess_LsuPlugin_dcache_st_w;
  wire       [31:0]   memaccess_LsuPlugin_dcache_wdata;
  wire       [3:0]    memaccess_LsuPlugin_dcache_wstrb;
  wire                memaccess_LsuPlugin_is_ale;
  reg                 memaccess_LsuPlugin_LLbit_data;
  reg                 memaccess_LsuPlugin_LLbit_we;
  wire                memaccess_LsuPlugin_is_sc;
  wire                memaccess_LsuPlugin_is_ll;
  reg                 tmp_memaccess_LsuPlugin_is_ale;
  reg        [31:0]   tmp_memaccess_LsuPlugin_dcache_data_load;
  reg        [1:0]    tmp_memaccess_LsuPlugin_lsu_size;
  reg        [31:0]   tmp_memaccess_LsuPlugin_dcache_wdata;
  reg        [3:0]    tmp_memaccess_LsuPlugin_dcache_wstrb;
  reg        [3:0]    tmp_memaccess_LsuPlugin_dcache_wstrb_1;
  reg        [3:0]    tmp_memaccess_LsuPlugin_dcache_wstrb_2;
  reg        [3:0]    tmp_memaccess_LsuPlugin_dcache_wstrb_3;
  reg        [3:0]    tmp_memaccess_LsuPlugin_dcache_wstrb_4;
  wire                dcache_stall;
  reg        [31:0]   fetch_to_decode_PC;
  reg        [31:0]   decode_to_execute_PC;
  reg        [31:0]   execute_to_memaccess_PC;
  reg        [31:0]   memaccess_to_writeback_PC;
  reg        [31:0]   fetch_to_decode_PC_NEXT;
  reg        [31:0]   fetch_to_decode_INSTRUCTION;
  reg        [31:0]   decode_to_execute_INSTRUCTION;
  reg        [31:0]   execute_to_memaccess_INSTRUCTION;
  reg        [31:0]   memaccess_to_writeback_INSTRUCTION;
  reg                 fetch_to_decode_PREDICT_TAKEN;
  reg                 fetch_to_decode_INT_PC;
  reg                 decode_to_execute_INT_PC;
  reg        [4:0]    decode_to_execute_ALU_CTRL;
  reg                 decode_to_execute_RD_WEN;
  reg                 execute_to_memaccess_RD_WEN;
  reg                 memaccess_to_writeback_RD_WEN;
  reg        [4:0]    decode_to_execute_RD_ADDR;
  reg        [4:0]    execute_to_memaccess_RD_ADDR;
  reg        [4:0]    memaccess_to_writeback_RD_ADDR;
  reg        [31:0]   decode_to_execute_RS1;
  reg        [31:0]   decode_to_execute_RS2;
  reg        [31:0]   decode_to_execute_LINK_ADDR;
  reg                 decode_to_execute_REDIRECT_VALID;
  reg        [31:0]   decode_to_execute_REDIRECT_PC_NEXT;
  reg        [3:0]    decode_to_execute_MEM_CTRL;
  reg        [3:0]    execute_to_memaccess_MEM_CTRL;
  reg                 decode_to_execute_IS_LOAD;
  reg                 execute_to_memaccess_IS_LOAD;
  reg                 decode_to_execute_IS_STORE;
  reg                 execute_to_memaccess_IS_STORE;
  reg        [31:0]   decode_to_execute_MEM_WDATA;
  reg        [31:0]   execute_to_memaccess_MEM_WDATA;
  reg        [3:0]    decode_to_execute_CSR_CTRL;
  reg        [13:0]   decode_to_execute_CSR_ADDR;
  reg                 decode_to_execute_CSR_WEN;
  reg                 decode_to_execute_IS_CSR;
  reg                 execute_to_memaccess_IS_CSR;
  reg        [14:0]   decode_to_execute_CSR_CODE;
  reg        [31:0]   decode_to_execute_CSR_RDATA;
  reg        [31:0]   execute_to_memaccess_CSR_RDATA;
  reg        [31:0]   execute_to_memaccess_ALU_RESULT;
  reg                 memaccess_to_writeback_LLBIT_WE;
  reg                 memaccess_to_writeback_LLBIT_DATA;
  reg        [31:0]   memaccess_to_writeback_RD;
  function [19:0] zz_tmp_decode_DecodePlugin_imm(input dummy);
    begin
      zz_tmp_decode_DecodePlugin_imm[19] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[18] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[17] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[16] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[15] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[14] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[13] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[12] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[11] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[10] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[9] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[8] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[7] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[6] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[5] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[4] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[3] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[2] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[1] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm[0] = 1'b0; // @ Literal.scala l87
    end
  endfunction
  wire [19:0] tmp_10;
  function [26:0] zz_tmp_decode_DecodePlugin_imm_3(input dummy);
    begin
      zz_tmp_decode_DecodePlugin_imm_3[26] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[25] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[24] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[23] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[22] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[21] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[20] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[19] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[18] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[17] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[16] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[15] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[14] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[13] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[12] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[11] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[10] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[9] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[8] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[7] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[6] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[5] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[4] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[3] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[2] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[1] = 1'b0; // @ Literal.scala l87
      zz_tmp_decode_DecodePlugin_imm_3[0] = 1'b0; // @ Literal.scala l87
    end
  endfunction
  wire [26:0] tmp_11;
  function [23:0] zz_tmp_memaccess_LsuPlugin_dcache_ld_bu(input dummy);
    begin
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[23] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[22] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[21] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[20] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[19] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[18] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[17] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[16] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[15] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[14] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[13] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[12] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[11] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[10] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[9] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[8] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[7] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[6] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[5] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[4] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[3] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[2] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[1] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_bu[0] = 1'b0; // @ Literal.scala l87
    end
  endfunction
  wire [23:0] tmp_12;
  function [15:0] zz_tmp_memaccess_LsuPlugin_dcache_ld_hu(input dummy);
    begin
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[15] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[14] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[13] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[12] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[11] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[10] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[9] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[8] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[7] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[6] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[5] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[4] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[3] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[2] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[1] = 1'b0; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_ld_hu[0] = 1'b0; // @ Literal.scala l87
    end
  endfunction
  wire [15:0] tmp_13;
  function [3:0] zz_tmp_memaccess_LsuPlugin_dcache_wstrb(input dummy);
    begin
      zz_tmp_memaccess_LsuPlugin_dcache_wstrb = 4'b0000; // @ BitVector.scala l486
      zz_tmp_memaccess_LsuPlugin_dcache_wstrb[0] = 1'b1; // @ Literal.scala l84
    end
  endfunction
  wire [3:0] tmp_14;
  function [3:0] zz_tmp_memaccess_LsuPlugin_dcache_wstrb_1(input dummy);
    begin
      zz_tmp_memaccess_LsuPlugin_dcache_wstrb_1 = 4'b0000; // @ BitVector.scala l486
      zz_tmp_memaccess_LsuPlugin_dcache_wstrb_1[1] = 1'b1; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_wstrb_1[0] = 1'b1; // @ Literal.scala l87
    end
  endfunction
  wire [3:0] tmp_15;
  function [3:0] zz_tmp_memaccess_LsuPlugin_dcache_wstrb_2(input dummy);
    begin
      zz_tmp_memaccess_LsuPlugin_dcache_wstrb_2[3] = 1'b1; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_wstrb_2[2] = 1'b1; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_wstrb_2[1] = 1'b1; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_wstrb_2[0] = 1'b1; // @ Literal.scala l87
    end
  endfunction
  wire [3:0] tmp_16;
  function [3:0] zz_tmp_memaccess_LsuPlugin_dcache_wstrb_3(input dummy);
    begin
      zz_tmp_memaccess_LsuPlugin_dcache_wstrb_3[3] = 1'b1; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_wstrb_3[2] = 1'b1; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_wstrb_3[1] = 1'b1; // @ Literal.scala l87
      zz_tmp_memaccess_LsuPlugin_dcache_wstrb_3[0] = 1'b1; // @ Literal.scala l87
    end
  endfunction
  wire [3:0] tmp_17;

  assign tmp_when_5 = (memaccess_LLBIT == 1'b0);
  assign tmp_when_3 = (decode_DecodePlugin_rd_addr == 5'h00);
  assign tmp_when_4 = ((decode_DecodePlugin_rs1_addr == 5'h01) && (decode_DecodePlugin_imm == 32'h00000000));
  assign tmp_when = (decode_DecodePlugin_is_jirl || decode_DecodePlugin_is_branch);
  assign tmp_when_1 = (decode_DecodePlugin_is_jirl || decode_DecodePlugin_fetch_dec_branch);
  assign tmp_when_2 = ((! decode_PREDICT_TAKEN) || (decode_PC_NEXT != decode_DecodePlugin_pc_next));
  assign tmp_8 = decode_INSTRUCTION[14 : 10];
  assign tmp_9 = decode_INSTRUCTION[14 : 10];
  assign tmp_pc_next_1 = (pc_next + 32'h00000004);
  assign tmp_decode_DecodePlugin_is_adef = decode_PC;
  assign tmp_tmp_decode_DecodePlugin_imm_8 = ($signed(tmp_tmp_decode_DecodePlugin_imm_8_1) + $signed(tmp_tmp_decode_DecodePlugin_imm_8_2));
  assign tmp_tmp_decode_DecodePlugin_imm_8_1 = {decode_INSTRUCTION[24 : 5],12'h000};
  assign tmp_tmp_decode_DecodePlugin_imm_8_2 = decode_PC;
  assign tmp_tmp_decode_RS1 = ($signed(tmp_tmp_decode_RS1_1) + $signed(tmp_tmp_decode_RS1_2));
  assign tmp_tmp_decode_RS1_1 = decode_DecodePlugin_rs1;
  assign tmp_tmp_decode_RS1_2 = decode_DecodePlugin_imm;
  assign tmp_decode_DecodePlugin_rs1_eq_rs2 = decode_RS1;
  assign tmp_decode_DecodePlugin_rs1_eq_rs2_1 = decode_RS2;
  assign tmp_decode_DecodePlugin_rs1_ne_rs2 = decode_RS1;
  assign tmp_decode_DecodePlugin_rs1_ne_rs2_1 = decode_RS2;
  assign tmp_decode_DecodePlugin_rs1_lt_rs2 = decode_RS1;
  assign tmp_decode_DecodePlugin_rs1_lt_rs2_1 = decode_RS2;
  assign tmp_decode_DecodePlugin_rs1_ge_rs2 = decode_RS2;
  assign tmp_decode_DecodePlugin_rs1_ge_rs2_1 = decode_RS1;
  assign tmp_tmp_decode_DecodePlugin_link_addr = ($signed(tmp_tmp_decode_DecodePlugin_link_addr_1) + $signed(32'h00000004));
  assign tmp_tmp_decode_DecodePlugin_link_addr_1 = decode_PC;
  assign tmp_tmp_decode_DecodePlugin_link_addr_2 = ($signed(tmp_tmp_decode_DecodePlugin_link_addr_3) + $signed(32'h00000004));
  assign tmp_tmp_decode_DecodePlugin_link_addr_3 = decode_PC;
  assign tmp_tmp_decode_DecodePlugin_pc_next = ($signed(tmp_tmp_decode_DecodePlugin_pc_next_1) + $signed(tmp_tmp_decode_DecodePlugin_pc_next_2));
  assign tmp_tmp_decode_DecodePlugin_pc_next_1 = decode_DecodePlugin_imm;
  assign tmp_tmp_decode_DecodePlugin_pc_next_2 = tmp_decode_RS1;
  assign tmp_tmp_decode_DecodePlugin_pc_next_3 = ($signed(tmp_tmp_decode_DecodePlugin_pc_next_4) + $signed(tmp_tmp_decode_DecodePlugin_pc_next_5));
  assign tmp_tmp_decode_DecodePlugin_pc_next_4 = decode_DecodePlugin_imm;
  assign tmp_tmp_decode_DecodePlugin_pc_next_5 = decode_PC;
  assign tmp_execute_AluPlugin_sub_result = execute_AluPlugin_src1;
  assign tmp_execute_AluPlugin_sub_result_1 = execute_AluPlugin_src2;
  assign tmp_execute_AluPlugin_sra_result = execute_AluPlugin_src1;
  assign tmp_execute_AluPlugin_add_result = execute_AluPlugin_src1;
  assign tmp_execute_AluPlugin_add_result_1 = execute_AluPlugin_src2;
  assign tmp_execute_AluPlugin_slt_result = execute_AluPlugin_src1;
  assign tmp_execute_AluPlugin_slt_result_1 = execute_AluPlugin_src2;
  assign tmp_memaccess_LsuPlugin_dcache_rdata = ({3'd0,memaccess_LsuPlugin_cpu_addr_sel} <<< 2'd3);
  assign tmp_tmp_memaccess_LsuPlugin_is_ale = memaccess_LsuPlugin_cpu_addr;
  assign tmp_tmp_memaccess_LsuPlugin_is_ale_1 = memaccess_LsuPlugin_cpu_addr;
  assign tmp_tmp_memaccess_LsuPlugin_is_ale_2 = memaccess_LsuPlugin_cpu_addr;
  assign tmp_tmp_memaccess_LsuPlugin_is_ale_3 = memaccess_LsuPlugin_cpu_addr;
  assign tmp_tmp_memaccess_LsuPlugin_is_ale_4 = memaccess_LsuPlugin_cpu_addr;
  assign tmp_tmp_memaccess_LsuPlugin_is_ale_5 = memaccess_LsuPlugin_cpu_addr;
  assign tmp_tmp_memaccess_LsuPlugin_is_ale_6 = memaccess_LsuPlugin_cpu_addr;
  assign tmp_memaccess_LsuPlugin_lsu_wdata = ({3'd0,memaccess_LsuPlugin_cpu_addr_sel} <<< 2'd3);
  FIFO fetch_FetchPlugin_pc_stream_fifo (
    .ports_s_ports_valid   (fetch_FetchPlugin_pc_in_stream_valid                        ), //i
    .ports_s_ports_ready   (fetch_FetchPlugin_pc_stream_fifo_ports_s_ports_ready        ), //o
    .ports_s_ports_payload (fetch_FetchPlugin_pc_in_stream_payload[31:0]                ), //i
    .ports_m_ports_valid   (fetch_FetchPlugin_pc_stream_fifo_ports_m_ports_valid        ), //o
    .ports_m_ports_ready   (fetch_FetchPlugin_pc_out_stream_ready                       ), //i
    .ports_m_ports_payload (fetch_FetchPlugin_pc_stream_fifo_ports_m_ports_payload[31:0]), //o
    .flush                 (fetch_arbitration_flushIt                                   ), //i
    .next_payload          (fetch_FetchPlugin_pc_stream_fifo_next_payload[31:0]         ), //o
    .next_valid            (fetch_FetchPlugin_pc_stream_fifo_next_valid                 ), //o
    .clk                   (clk                                                         ), //i
    .reset                 (reset                                                       )  //i
  );
  FIFO_1 fetch_FetchPlugin_predict_taken_fifo (
    .ports_s_ports_valid   (fetch_FetchPlugin_predict_taken_in_valid                  ), //i
    .ports_s_ports_ready   (fetch_FetchPlugin_predict_taken_fifo_ports_s_ports_ready  ), //o
    .ports_s_ports_payload (fetch_FetchPlugin_predict_taken_in_payload                ), //i
    .ports_m_ports_valid   (fetch_FetchPlugin_predict_taken_fifo_ports_m_ports_valid  ), //o
    .ports_m_ports_ready   (fetch_FetchPlugin_predict_taken_out_ready                 ), //i
    .ports_m_ports_payload (fetch_FetchPlugin_predict_taken_fifo_ports_m_ports_payload), //o
    .flush                 (fetch_arbitration_flushIt                                 ), //i
    .clk                   (clk                                                       ), //i
    .reset                 (reset                                                     )  //i
  );
  FIFO_2 fetch_FetchPlugin_instruction_stream_fifo (
    .ports_s_ports_valid   (fetch_FetchPlugin_instruction_in_stream_valid                        ), //i
    .ports_s_ports_ready   (fetch_FetchPlugin_instruction_stream_fifo_ports_s_ports_ready        ), //o
    .ports_s_ports_payload (fetch_FetchPlugin_instruction_in_stream_payload[31:0]                ), //i
    .ports_m_ports_valid   (fetch_FetchPlugin_instruction_stream_fifo_ports_m_ports_valid        ), //o
    .ports_m_ports_ready   (fetch_FetchPlugin_instruction_out_stream_ready                       ), //i
    .ports_m_ports_payload (fetch_FetchPlugin_instruction_stream_fifo_ports_m_ports_payload[31:0]), //o
    .flush                 (fetch_arbitration_flushIt                                            ), //i
    .clk                   (clk                                                                  ), //i
    .reset                 (reset                                                                )  //i
  );
  RegFileModule regFileModule_1 (
    .read_ports_rs1_value (regFileModule_1_read_ports_rs1_value[31:0]), //o
    .read_ports_rs2_value (regFileModule_1_read_ports_rs2_value[31:0]), //o
    .read_ports_rs1_addr  (decode_DecodePlugin_rs1_addr[4:0]         ), //i
    .read_ports_rs2_addr  (decode_DecodePlugin_rs2_addr[4:0]         ), //i
    .read_ports_rs1_req   (decode_DecodePlugin_rs1_req               ), //i
    .read_ports_rs2_req   (decode_DecodePlugin_rs2_req               ), //i
    .write_ports_rd_value (writeback_RD[31:0]                        ), //i
    .write_ports_rd_addr  (writeback_RD_ADDR[4:0]                    ), //i
    .write_ports_rd_wen   (regFileModule_1_write_ports_rd_wen        ), //i
    .clk                  (clk                                       ), //i
    .reset                (reset                                     )  //i
  );
  gshare_predictor gshare_predictor_1 (
    .predict_pc         (fetch_PREDICT_PC[31:0]                      ), //i
    .predict_valid      (fetch_PREDICT_VALID                         ), //i
    .predict_taken      (gshare_predictor_1_predict_taken            ), //o
    .predict_history    (gshare_predictor_1_predict_history[6:0]     ), //o
    .predict_pc_next    (gshare_predictor_1_predict_pc_next[31:0]    ), //o
    .train_pc           (tmp_decode_to_execute_PC[31:0]              ), //i
    .train_taken        (decode_BRANCH_TAKEN                         ), //i
    .train_valid        (decode_BRANCH_OR_JUMP                       ), //i
    .train_history      (decode_BRANCH_HISTORY[6:0]                  ), //i
    .train_mispredicted (tmp_fetch_arbitration_flushIt_2             ), //i
    .train_pc_next      (tmp_decode_to_execute_REDIRECT_PC_NEXT[31:0]), //i
    .train_is_call      (decode_IS_CALL                              ), //i
    .train_is_return    (decode_IS_RETURN                            ), //i
    .train_is_jump      (decode_IS_JUMP                              ), //i
    .clk                (clk                                         ), //i
    .reset              (reset                                       )  //i
  );
  CsrRegfile csrRegfile_1 (
    .cpu_ports_waddr      (csrRegfile_1_cpu_ports_waddr[13:0]  ), //i
    .cpu_ports_wen        (execute_CSR_WEN                     ), //i
    .cpu_ports_wdata      (execute_ExcepPlugin_csr_wdata[31:0] ), //i
    .cpu_ports_raddr      (csrRegfile_1_cpu_ports_raddr[13:0]  ), //i
    .cpu_ports_rdata      (csrRegfile_1_cpu_ports_rdata[31:0]  ), //o
    .cpu_ports_wvalid     (csrRegfile_1_cpu_ports_wvalid       ), //o
    .cpu_ports_is_ertn    (execute_ExcepPlugin_is_ertn         ), //i
    .cpu_ports_is_syscall (execute_ExcepPlugin_is_syscall      ), //i
    .cpu_ports_is_adef    (execute_ExcepPlugin_is_adef         ), //i
    .cpu_ports_is_ine     (execute_ExcepPlugin_is_ine          ), //i
    .cpu_ports_is_break   (execute_ExcepPlugin_is_break        ), //i
    .cpu_ports_is_ale     (tmp_fetch_arbitration_flushIt       ), //i
    .cpu_ports_int_pc     (csrRegfile_1_cpu_ports_int_pc       ), //o
    .cpu_ports_pc_next    (csrRegfile_1_cpu_ports_pc_next[31:0]), //o
    .cpu_ports_excep_pc   (execute_CSR_CODE[14:0]              ), //i
    .cpu_ports_pc         (csrRegfile_1_cpu_ports_pc[31:0]     ), //i
    .clk                  (clk                                 ), //i
    .reset                (reset                               )  //i
  );
  LLbitModule lLbitModule_1 (
    .read_ports_LLbit_data  (lLbitModule_1_read_ports_LLbit_data), //o
    .write_ports_LLbit_wen  (writeback_LLBIT_WE                 ), //i
    .write_ports_LLbit_data (writeback_LLBIT_DATA               ), //i
    .clk                    (clk                                ), //i
    .reset                  (reset                              )  //i
  );
  assign writeback_RD = memaccess_to_writeback_RD; // @ Stage.scala l30
  assign memaccess_RD = (memaccess_IS_LOAD ? memaccess_LSU_RDATA : (memaccess_IS_CSR ? memaccess_CSR_RDATA : memaccess_ALU_RESULT)); // @ Stage.scala l30
  assign memaccess_LSU_HOLD = DCachePlugin_dcache_access_stall; // @ Stage.scala l30
  assign memaccess_LLBIT_DATA = memaccess_LsuPlugin_LLbit_data; // @ Stage.scala l30
  assign memaccess_LLBIT_WE = memaccess_LsuPlugin_LLbit_we; // @ Stage.scala l30
  assign memaccess_IS_ALE = memaccess_LsuPlugin_is_ale; // @ Stage.scala l30
  assign execute_ALU_RESULT = execute_AluPlugin_alu_result; // @ Stage.scala l30
  assign decode_CSR_RDATA = csrRegfile_1_cpu_ports_rdata; // @ Stage.scala l30
  assign decode_CSR_CODE = decode_DecodePlugin_csr_code; // @ Stage.scala l30
  assign execute_IS_CSR = decode_to_execute_IS_CSR; // @ Stage.scala l30
  assign decode_IS_CSR = decode_DecodePlugin_is_csr; // @ Stage.scala l30
  assign decode_CSR_WEN = decode_DecodePlugin_csr_wen; // @ Stage.scala l30
  assign decode_CSR_CTRL = decode_DecodePlugin_csr_ctrl; // @ Stage.scala l30
  assign execute_MEM_WDATA = decode_to_execute_MEM_WDATA; // @ Stage.scala l30
  assign decode_MEM_WDATA = decode_DecodePlugin_mem_wdata; // @ Stage.scala l30
  assign execute_IS_STORE = decode_to_execute_IS_STORE; // @ Stage.scala l30
  assign decode_IS_STORE = decode_DecodePlugin_is_store; // @ Stage.scala l30
  assign decode_IS_LOAD = decode_DecodePlugin_is_load; // @ Stage.scala l30
  assign execute_MEM_CTRL = decode_to_execute_MEM_CTRL; // @ Stage.scala l30
  assign decode_MEM_CTRL = decode_DecodePlugin_mem_ctrl; // @ Stage.scala l30
  assign decode_BRANCH_HISTORY = decode_DecodePlugin_branch_history; // @ Stage.scala l30
  assign decode_IS_RETURN = decode_DecodePlugin_is_return; // @ Stage.scala l30
  assign decode_IS_JUMP = decode_DecodePlugin_is_jump; // @ Stage.scala l30
  assign decode_IS_CALL = decode_DecodePlugin_is_call; // @ Stage.scala l30
  assign execute_REDIRECT_PC_NEXT = decode_to_execute_REDIRECT_PC_NEXT; // @ Stage.scala l30
  assign decode_REDIRECT_PC_NEXT = decode_DecodePlugin_redirect_pc_next; // @ Stage.scala l30
  assign execute_REDIRECT_VALID = decode_to_execute_REDIRECT_VALID; // @ Stage.scala l30
  assign decode_REDIRECT_VALID = decode_DecodePlugin_redirect_valid; // @ Stage.scala l30
  assign decode_LINK_ADDR = decode_DecodePlugin_link_addr; // @ Stage.scala l30
  assign decode_BRANCH_TAKEN = (decode_DecodePlugin_is_jirl || decode_DecodePlugin_fetch_dec_branch); // @ Stage.scala l30
  assign decode_BRANCH_OR_JUMP = ((decode_DecodePlugin_is_jirl || decode_DecodePlugin_is_branch) && decode_arbitration_isFiring); // @ Stage.scala l30
  assign writeback_RD_ADDR = memaccess_to_writeback_RD_ADDR; // @ Stage.scala l30
  assign memaccess_RD_ADDR = execute_to_memaccess_RD_ADDR; // @ Stage.scala l30
  assign execute_RD_ADDR = decode_to_execute_RD_ADDR; // @ Stage.scala l30
  assign decode_RD_ADDR = decode_DecodePlugin_rd_addr; // @ Stage.scala l30
  assign writeback_RD_WEN = memaccess_to_writeback_RD_WEN; // @ Stage.scala l30
  assign memaccess_RD_WEN = execute_to_memaccess_RD_WEN; // @ Stage.scala l30
  assign execute_RD_WEN = decode_to_execute_RD_WEN; // @ Stage.scala l30
  assign decode_RD_WEN = decode_DecodePlugin_rd_wen; // @ Stage.scala l30
  assign decode_ALU_CTRL = decode_DecodePlugin_alu_ctrl; // @ Stage.scala l30
  assign execute_INT_PC = decode_to_execute_INT_PC; // @ Stage.scala l30
  assign decode_INT_PC = fetch_to_decode_INT_PC; // @ Stage.scala l30
  assign fetch_PREDICT_PC = pc_next; // @ Stage.scala l30
  assign fetch_PREDICT_TAKEN = fetch_FetchPlugin_predict_taken_out_payload; // @ Stage.scala l30
  assign fetch_PREDICT_VALID = ICachePlugin_icache_access_cmd_fire; // @ Stage.scala l30
  assign memaccess_INSTRUCTION = execute_to_memaccess_INSTRUCTION; // @ Stage.scala l30
  assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; // @ Stage.scala l30
  assign fetch_INSTRUCTION = fetch_FetchPlugin_instruction_out_stream_payload; // @ Stage.scala l30
  assign fetch_PC_NEXT = fetch_FetchPlugin_pc_stream_fifo_next_payload; // @ Stage.scala l30
  assign memaccess_PC = execute_to_memaccess_PC; // @ Stage.scala l30
  assign fetch_PC = fetch_FetchPlugin_pc_out_stream_payload; // @ Stage.scala l30
  assign writeback_INSTRUCTION = memaccess_to_writeback_INSTRUCTION; // @ Stage.scala l30
  assign writeback_PC = memaccess_to_writeback_PC; // @ Stage.scala l30
  assign writeback_LLBIT_WE = memaccess_to_writeback_LLBIT_WE; // @ Stage.scala l30
  assign writeback_LLBIT_DATA = memaccess_to_writeback_LLBIT_DATA; // @ Stage.scala l30
  assign memaccess_CSR_RDATA = execute_to_memaccess_CSR_RDATA; // @ Stage.scala l30
  assign memaccess_IS_CSR = execute_to_memaccess_IS_CSR; // @ Stage.scala l30
  assign memaccess_LSU_RDATA = memaccess_LsuPlugin_lsu_rdata; // @ Stage.scala l30
  assign memaccess_MEM_CTRL = execute_to_memaccess_MEM_CTRL; // @ Stage.scala l30
  assign memaccess_LLBIT = lLbitModule_1_read_ports_LLbit_data; // @ Stage.scala l30
  assign memaccess_MEM_WDATA = execute_to_memaccess_MEM_WDATA; // @ Stage.scala l30
  assign memaccess_IS_LOAD = execute_to_memaccess_IS_LOAD; // @ Stage.scala l30
  always @(*) begin
    memaccess_IS_STORE = execute_to_memaccess_IS_STORE; // @ Stage.scala l30
    if(memaccess_LsuPlugin_is_sc) begin
      if(tmp_when_5) begin
        memaccess_IS_STORE = 1'b0; // @ LsuPlugin.scala l92
      end
    end
  end

  assign memaccess_ALU_RESULT = execute_to_memaccess_ALU_RESULT; // @ Stage.scala l30
  assign execute_CSR_WEN = decode_to_execute_CSR_WEN; // @ Stage.scala l30
  assign execute_PC = decode_to_execute_PC; // @ Stage.scala l30
  assign execute_CSR_ADDR = decode_to_execute_CSR_ADDR; // @ Stage.scala l30
  assign execute_CSR_CODE = decode_to_execute_CSR_CODE; // @ Stage.scala l30
  assign execute_CSR_CTRL = decode_to_execute_CSR_CTRL; // @ Stage.scala l30
  assign execute_CSR_RDATA = decode_to_execute_CSR_RDATA; // @ Stage.scala l30
  assign decode_CSR_ADDR = decode_DecodePlugin_csr_addr; // @ Stage.scala l30
  assign tmp_memaccess_arbitration_haltItself = memaccess_LSU_HOLD; // @ Stage.scala l39
  assign execute_IS_LOAD = decode_to_execute_IS_LOAD; // @ Stage.scala l30
  assign tmp_fetch_arbitration_flushIt = memaccess_IS_ALE; // @ Stage.scala l39
  assign tmp_fetch_arbitration_flushIt_1 = execute_INT_PC; // @ Stage.scala l39
  assign tmp_DecodePlugin_hazard_rs1_from_ex = execute_RD_ADDR; // @ Stage.scala l39
  assign tmp_DecodePlugin_hazard_rs1_from_ex_1 = execute_RD_WEN; // @ Stage.scala l39
  assign decode_RS2_REQ = decode_DecodePlugin_rs2_req; // @ Stage.scala l30
  assign decode_RS2_ADDR = decode_DecodePlugin_rs2_addr; // @ Stage.scala l30
  assign decode_RS1_REQ = decode_DecodePlugin_rs1_req; // @ Stage.scala l30
  assign decode_RS1_ADDR = decode_DecodePlugin_rs1_addr; // @ Stage.scala l30
  assign tmp_DecodePlugin_hazard_rs1_from_mem = memaccess_RD_ADDR; // @ Stage.scala l39
  assign tmp_DecodePlugin_hazard_rs1_from_mem_1 = memaccess_RD_WEN; // @ Stage.scala l39
  assign execute_LINK_ADDR = decode_to_execute_LINK_ADDR; // @ Stage.scala l30
  assign execute_ALU_CTRL = decode_to_execute_ALU_CTRL; // @ Stage.scala l30
  assign execute_RS2 = decode_to_execute_RS2; // @ Stage.scala l30
  assign execute_RS1 = decode_to_execute_RS1; // @ Stage.scala l30
  assign tmp_decode_to_execute_REDIRECT_PC_NEXT = decode_REDIRECT_PC_NEXT; // @ Stage.scala l39
  assign tmp_decode_to_execute_PC = decode_PC; // @ Stage.scala l39
  assign tmp_fetch_arbitration_flushIt_2 = decode_REDIRECT_VALID; // @ Stage.scala l39
  assign decode_PC_NEXT = fetch_to_decode_PC_NEXT; // @ Stage.scala l30
  assign decode_PREDICT_TAKEN = fetch_to_decode_PREDICT_TAKEN; // @ Stage.scala l30
  assign decode_RS2 = tmp_decode_RS2; // @ Stage.scala l30
  assign decode_RS1 = tmp_decode_RS1; // @ Stage.scala l30
  assign decode_RS2_FROM_MEM = DecodePlugin_hazard_rs2_from_mem; // @ Stage.scala l30
  assign decode_RS2_FROM_EX = DecodePlugin_hazard_rs2_from_ex; // @ Stage.scala l30
  assign tmp_memaccess_to_writeback_RD = memaccess_RD; // @ Stage.scala l39
  assign decode_RS1_FROM_MEM = DecodePlugin_hazard_rs1_from_mem; // @ Stage.scala l30
  assign tmp_execute_to_memaccess_ALU_RESULT = execute_ALU_RESULT; // @ Stage.scala l39
  assign decode_RS1_FROM_EX = DecodePlugin_hazard_rs1_from_ex; // @ Stage.scala l30
  assign decode_INSTRUCTION = fetch_to_decode_INSTRUCTION; // @ Stage.scala l30
  assign decode_PC = fetch_to_decode_PC; // @ Stage.scala l30
  assign fetch_BPU_PC_NEXT = gshare_predictor_1_predict_pc_next; // @ Stage.scala l30
  assign fetch_CSR_PC = csrRegfile_1_cpu_ports_pc_next; // @ Stage.scala l30
  assign fetch_INT_PC = csrRegfile_1_cpu_ports_int_pc; // @ Stage.scala l30
  assign tmp_pc_next = execute_REDIRECT_VALID; // @ Stage.scala l39
  assign fetch_BPU_BRANCH_TAKEN = gshare_predictor_1_predict_taken; // @ Stage.scala l30
  assign fetch_arbitration_haltByOther = 1'b0; // @ Stage.scala l51
  always @(*) begin
    fetch_arbitration_removeIt = 1'b0; // @ Stage.scala l52
    if(fetch_arbitration_isFlushed) begin
      fetch_arbitration_removeIt = 1'b1; // @ Pipeline.scala l137
    end
  end

  assign fetch_arbitration_flushNext = 1'b0; // @ Stage.scala l54
  assign decode_arbitration_haltByOther = 1'b0; // @ Stage.scala l51
  always @(*) begin
    decode_arbitration_removeIt = 1'b0; // @ Stage.scala l52
    if(decode_arbitration_isFlushed) begin
      decode_arbitration_removeIt = 1'b1; // @ Pipeline.scala l137
    end
  end

  assign decode_arbitration_flushNext = 1'b0; // @ Stage.scala l54
  assign execute_arbitration_haltByOther = 1'b0; // @ Stage.scala l51
  always @(*) begin
    execute_arbitration_removeIt = 1'b0; // @ Stage.scala l52
    if(execute_arbitration_isFlushed) begin
      execute_arbitration_removeIt = 1'b1; // @ Pipeline.scala l137
    end
  end

  assign execute_arbitration_flushNext = 1'b0; // @ Stage.scala l54
  assign memaccess_arbitration_haltByOther = 1'b0; // @ Stage.scala l51
  always @(*) begin
    memaccess_arbitration_removeIt = 1'b0; // @ Stage.scala l52
    if(memaccess_arbitration_isFlushed) begin
      memaccess_arbitration_removeIt = 1'b1; // @ Pipeline.scala l137
    end
  end

  assign memaccess_arbitration_flushNext = 1'b0; // @ Stage.scala l54
  assign writeback_arbitration_haltByOther = 1'b0; // @ Stage.scala l51
  always @(*) begin
    writeback_arbitration_removeIt = 1'b0; // @ Stage.scala l52
    if(writeback_arbitration_isFlushed) begin
      writeback_arbitration_removeIt = 1'b1; // @ Pipeline.scala l137
    end
  end

  assign writeback_arbitration_flushNext = 1'b0; // @ Stage.scala l54
  assign ICachePlugin_icache_access_cmd_fire = (ICachePlugin_icache_access_cmd_valid && ICachePlugin_icache_access_cmd_ready); // @ BaseType.scala l305
  assign fetch_FetchPlugin_bpu_predict_taken = (fetch_BPU_BRANCH_TAKEN && ICachePlugin_icache_access_cmd_fire); // @ BaseType.scala l305
  assign fetch_FetchPlugin_fifo_all_valid = ((fetch_FetchPlugin_pc_out_stream_valid && fetch_FetchPlugin_instruction_out_stream_valid) && fetch_FetchPlugin_pc_stream_fifo_next_valid); // @ BaseType.scala l305
  assign IDLE = 2'b00; // @ Expression.scala l2360
  assign FETCH = 2'b01; // @ Expression.scala l2360
  assign HALT = 2'b11; // @ Expression.scala l2360
  assign ICachePlugin_icache_access_cmd_isStall = (ICachePlugin_icache_access_cmd_valid && (! ICachePlugin_icache_access_cmd_ready)); // @ BaseType.scala l305
  always @(*) begin
    if((fetch_state == IDLE)) begin
        tmp_fetch_state_next = (fetch_arbitration_isStuck ? IDLE : FETCH); // @ Misc.scala l254
    end else if((fetch_state == FETCH)) begin
        tmp_fetch_state_next = ((ICachePlugin_icache_access_cmd_isStall || fetch_arbitration_isStuck) ? HALT : FETCH); // @ Misc.scala l254
    end else if((fetch_state == HALT)) begin
        tmp_fetch_state_next = ((ICachePlugin_icache_access_cmd_ready && (! fetch_arbitration_isStuck)) ? FETCH : HALT); // @ Misc.scala l254
    end else begin
        tmp_fetch_state_next = IDLE; // @ Misc.scala l250
    end
  end

  assign fetch_state_next = tmp_fetch_state_next; // @ FetchPlugin.scala l58
  assign fetch_FetchPlugin_pc_in_stream_valid = ICachePlugin_icache_access_cmd_fire; // @ FetchPlugin.scala l76
  assign fetch_FetchPlugin_pc_in_stream_payload = pc_next; // @ FetchPlugin.scala l77
  assign fetch_FetchPlugin_pc_out_stream_ready = fetch_arbitration_isFiring; // @ FetchPlugin.scala l78
  assign fetch_FetchPlugin_pc_in_stream_ready = fetch_FetchPlugin_pc_stream_fifo_ports_s_ports_ready; // @ FetchPlugin.scala l79
  assign fetch_FetchPlugin_pc_out_stream_valid = fetch_FetchPlugin_pc_stream_fifo_ports_m_ports_valid; // @ FetchPlugin.scala l80
  assign fetch_FetchPlugin_pc_out_stream_payload = fetch_FetchPlugin_pc_stream_fifo_ports_m_ports_payload; // @ FetchPlugin.scala l80
  assign fetch_FetchPlugin_predict_taken_in_valid = ICachePlugin_icache_access_cmd_fire; // @ FetchPlugin.scala l83
  assign fetch_FetchPlugin_predict_taken_in_payload = fetch_BPU_BRANCH_TAKEN; // @ FetchPlugin.scala l84
  assign fetch_FetchPlugin_predict_taken_out_ready = fetch_arbitration_isFiring; // @ FetchPlugin.scala l85
  assign fetch_FetchPlugin_predict_taken_in_ready = fetch_FetchPlugin_predict_taken_fifo_ports_s_ports_ready; // @ FetchPlugin.scala l86
  assign fetch_FetchPlugin_predict_taken_out_valid = fetch_FetchPlugin_predict_taken_fifo_ports_m_ports_valid; // @ FetchPlugin.scala l87
  assign fetch_FetchPlugin_predict_taken_out_payload = fetch_FetchPlugin_predict_taken_fifo_ports_m_ports_payload; // @ FetchPlugin.scala l87
  assign fetch_FetchPlugin_instruction_in_stream_valid = ((ICachePlugin_icache_access_rsp_valid && (! rsp_flush)) && (! fetch_arbitration_flushIt)); // @ FetchPlugin.scala l90
  assign fetch_FetchPlugin_instruction_in_stream_payload = ICachePlugin_icache_access_rsp_payload_data; // @ FetchPlugin.scala l91
  assign fetch_FetchPlugin_instruction_out_stream_ready = fetch_arbitration_isFiring; // @ FetchPlugin.scala l92
  assign fetch_FetchPlugin_instruction_in_stream_ready = fetch_FetchPlugin_instruction_stream_fifo_ports_s_ports_ready; // @ FetchPlugin.scala l93
  assign fetch_FetchPlugin_instruction_out_stream_valid = fetch_FetchPlugin_instruction_stream_fifo_ports_m_ports_valid; // @ FetchPlugin.scala l94
  assign fetch_FetchPlugin_instruction_out_stream_payload = fetch_FetchPlugin_instruction_stream_fifo_ports_m_ports_payload; // @ FetchPlugin.scala l94
  assign fetch_arbitration_isValid = ((fetch_FetchPlugin_fifo_all_valid && (! fetch_arbitration_isStuck)) && (! fetch_arbitration_flushIt)); // @ FetchPlugin.scala l103
  assign ICachePlugin_icache_access_cmd_valid = (fetch_valid && (! fetch_arbitration_flushIt)); // @ FetchPlugin.scala l105
  assign ICachePlugin_icache_access_cmd_payload_addr = pc_next; // @ FetchPlugin.scala l106
  always @(*) begin
    decode_DecodePlugin_is_call = 1'b0; // @ DecodePlugin.scala l99
    if(decode_DecodePlugin_is_jirl) begin
      if(tmp_when_3) begin
        if(tmp_when_4) begin
          decode_DecodePlugin_is_call = 1'b0; // @ DecodePlugin.scala l481
        end else begin
          decode_DecodePlugin_is_call = 1'b0; // @ DecodePlugin.scala l485
        end
      end else begin
        decode_DecodePlugin_is_call = 1'b1; // @ DecodePlugin.scala l489
      end
    end else begin
      if(decode_DecodePlugin_is_bl) begin
        decode_DecodePlugin_is_call = 1'b1; // @ DecodePlugin.scala l494
      end else begin
        decode_DecodePlugin_is_call = 1'b0; // @ DecodePlugin.scala l498
      end
    end
  end

  always @(*) begin
    decode_DecodePlugin_is_return = 1'b0; // @ DecodePlugin.scala l100
    if(decode_DecodePlugin_is_jirl) begin
      if(tmp_when_3) begin
        if(tmp_when_4) begin
          decode_DecodePlugin_is_return = 1'b1; // @ DecodePlugin.scala l480
        end else begin
          decode_DecodePlugin_is_return = 1'b0; // @ DecodePlugin.scala l486
        end
      end else begin
        decode_DecodePlugin_is_return = 1'b0; // @ DecodePlugin.scala l491
      end
    end else begin
      if(decode_DecodePlugin_is_bl) begin
        decode_DecodePlugin_is_return = 1'b0; // @ DecodePlugin.scala l496
      end else begin
        decode_DecodePlugin_is_return = 1'b0; // @ DecodePlugin.scala l500
      end
    end
  end

  always @(*) begin
    decode_DecodePlugin_is_jump = 1'b0; // @ DecodePlugin.scala l101
    if(decode_DecodePlugin_is_jirl) begin
      if(tmp_when_3) begin
        if(tmp_when_4) begin
          decode_DecodePlugin_is_jump = 1'b0; // @ DecodePlugin.scala l482
        end else begin
          decode_DecodePlugin_is_jump = 1'b1; // @ DecodePlugin.scala l484
        end
      end else begin
        decode_DecodePlugin_is_jump = 1'b0; // @ DecodePlugin.scala l490
      end
    end else begin
      if(decode_DecodePlugin_is_bl) begin
        decode_DecodePlugin_is_jump = 1'b0; // @ DecodePlugin.scala l495
      end else begin
        decode_DecodePlugin_is_jump = 1'b1; // @ DecodePlugin.scala l499
      end
    end
  end

  always @(*) begin
    decode_DecodePlugin_redirect_pc_next = (decode_PC + 32'h00000004); // @ BaseType.scala l299
    if(tmp_when) begin
      if(tmp_when_1) begin
        if(tmp_when_2) begin
          decode_DecodePlugin_redirect_pc_next = decode_DecodePlugin_pc_next; // @ DecodePlugin.scala l469
        end
      end else begin
        decode_DecodePlugin_redirect_pc_next = (decode_PC + 32'h00000004); // @ DecodePlugin.scala l473
      end
    end
  end

  always @(*) begin
    decode_DecodePlugin_redirect_valid = 1'b0; // @ DecodePlugin.scala l104
    if(tmp_when) begin
      if(tmp_when_1) begin
        if(tmp_when_2) begin
          decode_DecodePlugin_redirect_valid = 1'b1; // @ DecodePlugin.scala l468
        end
      end else begin
        decode_DecodePlugin_redirect_valid = 1'b1; // @ DecodePlugin.scala l472
      end
    end
  end

  assign decode_DecodePlugin_is_adef = (tmp_decode_DecodePlugin_is_adef[1 : 0] != 2'b00); // @ BaseType.scala l305
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b0000001101?????????????????????? : begin
        tmp_1 = 1'b1; // @ Misc.scala l254
      end
      32'b0000001110?????????????????????? : begin
        tmp_1 = 1'b1; // @ Misc.scala l254
      end
      32'b0000001111?????????????????????? : begin
        tmp_1 = 1'b1; // @ Misc.scala l254
      end
      default : begin
        tmp_1 = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  assign tmp_10 = zz_tmp_decode_DecodePlugin_imm(1'b0);
  always @(*) tmp_decode_DecodePlugin_imm = tmp_10;
  always @(*) begin
    if(tmp_1) begin
      decode_DecodePlugin_imm = {tmp_decode_DecodePlugin_imm,decode_INSTRUCTION[21 : 10]}; // @ DecodePlugin.scala l120
    end else begin
      if(tmp_2) begin
        decode_DecodePlugin_imm = {tmp_decode_DecodePlugin_imm_2,decode_INSTRUCTION[21 : 10]}; // @ DecodePlugin.scala l122
      end else begin
        if(tmp_3) begin
          decode_DecodePlugin_imm = {tmp_decode_DecodePlugin_imm_3,decode_INSTRUCTION[14 : 10]}; // @ DecodePlugin.scala l124
        end else begin
          if(tmp_4) begin
            decode_DecodePlugin_imm = {tmp_decode_DecodePlugin_imm_5,decode_INSTRUCTION[25 : 10]}; // @ DecodePlugin.scala l126
          end else begin
            if(tmp_5) begin
              decode_DecodePlugin_imm = {{decode_INSTRUCTION[9 : 0],decode_INSTRUCTION[25 : 10]},6'h00}; // @ DecodePlugin.scala l128
            end else begin
              if(tmp_6) begin
                decode_DecodePlugin_imm = {tmp_decode_DecodePlugin_imm_7,decode_INSTRUCTION[23 : 10]}; // @ DecodePlugin.scala l130
              end else begin
                if(tmp_7) begin
                  decode_DecodePlugin_imm = tmp_decode_DecodePlugin_imm_8; // @ DecodePlugin.scala l132
                end else begin
                  decode_DecodePlugin_imm = 32'h00000000; // @ DecodePlugin.scala l138
                end
              end
            end
          end
        end
      end
    end
  end

  assign tmp_decode_DecodePlugin_imm_1 = decode_INSTRUCTION[21]; // @ BaseType.scala l305
  always @(*) begin
    tmp_decode_DecodePlugin_imm_2[19] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[18] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[17] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[16] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[15] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[14] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[13] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[12] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[11] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[10] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[9] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[8] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[7] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[6] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[5] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[4] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[3] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[2] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[1] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_2[0] = tmp_decode_DecodePlugin_imm_1; // @ Literal.scala l87
  end

  assign tmp_11 = zz_tmp_decode_DecodePlugin_imm_3(1'b0);
  always @(*) tmp_decode_DecodePlugin_imm_3 = tmp_11;
  assign tmp_decode_DecodePlugin_imm_4 = decode_INSTRUCTION[25]; // @ BaseType.scala l305
  always @(*) begin
    tmp_decode_DecodePlugin_imm_5[15] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[14] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[13] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[12] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[11] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[10] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[9] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[8] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[7] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[6] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[5] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[4] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[3] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[2] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[1] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_5[0] = tmp_decode_DecodePlugin_imm_4; // @ Literal.scala l87
  end

  assign tmp_decode_DecodePlugin_imm_6 = decode_INSTRUCTION[23]; // @ BaseType.scala l305
  always @(*) begin
    tmp_decode_DecodePlugin_imm_7[17] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[16] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[15] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[14] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[13] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[12] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[11] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[10] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[9] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[8] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[7] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[6] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[5] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[4] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[3] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[2] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[1] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
    tmp_decode_DecodePlugin_imm_7[0] = tmp_decode_DecodePlugin_imm_6; // @ Literal.scala l87
  end

  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b0001010????????????????????????? : begin
        tmp_decode_DecodePlugin_imm_8 = {decode_INSTRUCTION[24 : 5],12'h000}; // @ Misc.scala l254
      end
      32'b0001110????????????????????????? : begin
        tmp_decode_DecodePlugin_imm_8 = tmp_tmp_decode_DecodePlugin_imm_8; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_imm_8 = 32'h00000000; // @ Misc.scala l250
      end
    endcase
  end

  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b0000001000?????????????????????? : begin
        tmp_2 = 1'b1; // @ Misc.scala l254
      end
      32'b0000001001?????????????????????? : begin
        tmp_2 = 1'b1; // @ Misc.scala l254
      end
      32'b0000001010?????????????????????? : begin
        tmp_2 = 1'b1; // @ Misc.scala l254
      end
      32'b0010100000?????????????????????? : begin
        tmp_2 = 1'b1; // @ Misc.scala l254
      end
      32'b0010100001?????????????????????? : begin
        tmp_2 = 1'b1; // @ Misc.scala l254
      end
      32'b0010100010?????????????????????? : begin
        tmp_2 = 1'b1; // @ Misc.scala l254
      end
      32'b0010100100?????????????????????? : begin
        tmp_2 = 1'b1; // @ Misc.scala l254
      end
      32'b0010100101?????????????????????? : begin
        tmp_2 = 1'b1; // @ Misc.scala l254
      end
      32'b0010100110?????????????????????? : begin
        tmp_2 = 1'b1; // @ Misc.scala l254
      end
      32'b0010101000?????????????????????? : begin
        tmp_2 = 1'b1; // @ Misc.scala l254
      end
      32'b0010101001?????????????????????? : begin
        tmp_2 = 1'b1; // @ Misc.scala l254
      end
      default : begin
        tmp_2 = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b00000000010000001??????????????? : begin
        tmp_3 = 1'b1; // @ Misc.scala l254
      end
      32'b00000000010001001??????????????? : begin
        tmp_3 = 1'b1; // @ Misc.scala l254
      end
      32'b00000000010010001??????????????? : begin
        tmp_3 = 1'b1; // @ Misc.scala l254
      end
      default : begin
        tmp_3 = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b010011?????????????????????????? : begin
        tmp_4 = 1'b1; // @ Misc.scala l254
      end
      32'b010110?????????????????????????? : begin
        tmp_4 = 1'b1; // @ Misc.scala l254
      end
      32'b010111?????????????????????????? : begin
        tmp_4 = 1'b1; // @ Misc.scala l254
      end
      32'b011000?????????????????????????? : begin
        tmp_4 = 1'b1; // @ Misc.scala l254
      end
      32'b011001?????????????????????????? : begin
        tmp_4 = 1'b1; // @ Misc.scala l254
      end
      32'b011010?????????????????????????? : begin
        tmp_4 = 1'b1; // @ Misc.scala l254
      end
      32'b011011?????????????????????????? : begin
        tmp_4 = 1'b1; // @ Misc.scala l254
      end
      default : begin
        tmp_4 = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b010100?????????????????????????? : begin
        tmp_5 = 1'b1; // @ Misc.scala l254
      end
      32'b010101?????????????????????????? : begin
        tmp_5 = 1'b1; // @ Misc.scala l254
      end
      default : begin
        tmp_5 = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b00100000???????????????????????? : begin
        tmp_6 = 1'b1; // @ Misc.scala l254
      end
      32'b00100001???????????????????????? : begin
        tmp_6 = 1'b1; // @ Misc.scala l254
      end
      default : begin
        tmp_6 = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b0001010????????????????????????? : begin
        tmp_7 = 1'b1; // @ Misc.scala l254
      end
      default : begin
        tmp_7 = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b0000001110?????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_OR_1; // @ Misc.scala l254
      end
      32'b0000001101?????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_AND_1; // @ Misc.scala l254
      end
      32'b0000001111?????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_XOR_1; // @ Misc.scala l254
      end
      32'b00000000000100000??????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_ADD; // @ Misc.scala l254
      end
      32'b0000001010?????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_ADD; // @ Misc.scala l254
      end
      32'b00000000000100010??????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_SUB; // @ Misc.scala l254
      end
      32'b00000000000101000??????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_NOR_1; // @ Misc.scala l254
      end
      32'b00000000000101001??????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_AND_1; // @ Misc.scala l254
      end
      32'b00000000000101010??????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_OR_1; // @ Misc.scala l254
      end
      32'b00000000000101011??????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_XOR_1; // @ Misc.scala l254
      end
      32'b00000000000101110??????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_SLL_1; // @ Misc.scala l254
      end
      32'b00000000000101111??????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_SRL_1; // @ Misc.scala l254
      end
      32'b00000000000110000??????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_SRA_1; // @ Misc.scala l254
      end
      32'b00000000010000001??????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_SLL_1; // @ Misc.scala l254
      end
      32'b00000000010001001??????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_SRL_1; // @ Misc.scala l254
      end
      32'b00000000010010001??????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_SRA_1; // @ Misc.scala l254
      end
      32'b00000000000100100??????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_SLT; // @ Misc.scala l254
      end
      32'b00000000000100101??????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_SLTU; // @ Misc.scala l254
      end
      32'b010011?????????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_JIRL; // @ Misc.scala l254
      end
      32'b0001010????????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_ADD; // @ Misc.scala l254
      end
      32'b0001110????????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_ADD; // @ Misc.scala l254
      end
      32'b010101?????????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_BL; // @ Misc.scala l254
      end
      32'b0010100000?????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_ADD; // @ Misc.scala l254
      end
      32'b0010101000?????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_ADD; // @ Misc.scala l254
      end
      32'b0010100001?????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_ADD; // @ Misc.scala l254
      end
      32'b0010101001?????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_ADD; // @ Misc.scala l254
      end
      32'b0010100010?????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_ADD; // @ Misc.scala l254
      end
      32'b0010100100?????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_ADD; // @ Misc.scala l254
      end
      32'b0010100110?????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_ADD; // @ Misc.scala l254
      end
      32'b0010100101?????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_ADD; // @ Misc.scala l254
      end
      32'b00100000???????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_ADD; // @ Misc.scala l254
      end
      32'b00100001???????????????????????? : begin
        tmp_decode_DecodePlugin_alu_ctrl = AluCtrlEnum_ADD; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_alu_ctrl = 5'h00; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_alu_ctrl = tmp_decode_DecodePlugin_alu_ctrl; // @ DecodePlugin.scala l142
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b0000001110?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b0000001101?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b0000001111?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000000000100000??????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b0000001010?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000000000100010??????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000000000101000??????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000000000101001??????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000000000101010??????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000000000101011??????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000000000101110??????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000000000101111??????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000000000110000??????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000000010000001??????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000000010001001??????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000000010010001??????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000000000100100??????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000000000100101??????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b010011?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b010110?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b010111?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b011000?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b011010?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b011001?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b011011?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b0010100000?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b0010100001?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b0010101000?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b0010101001?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b0010100010?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b0010100100?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b0010100110?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b0010100101?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00100000???????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00100001???????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_addr = decode_INSTRUCTION[9 : 5]; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_rs1_addr = 5'h00; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_rs1_addr = tmp_decode_DecodePlugin_rs1_addr; // @ DecodePlugin.scala l178
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b0000001110?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b0000001101?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b0000001111?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000100000??????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b0000001010?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000100010??????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101000??????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101001??????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101010??????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101011??????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101110??????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101111??????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000110000??????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000010000001??????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000010001001??????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000010010001??????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000100100??????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000100101??????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b010011?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b0001010????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b0001110????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b010110?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b010111?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b011000?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b011010?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b011001?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b011011?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b0010100000?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b0010101000?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b0010100001?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b0010101001?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b0010100010?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b0010100100?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b0010100110?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b0010100101?????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00100000???????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00100001???????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b1; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_rs1_req = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_rs1_req = tmp_decode_DecodePlugin_rs1_req; // @ DecodePlugin.scala l219
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b00000000000100000??????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[14 : 10]; // @ Misc.scala l254
      end
      32'b00000000000100010??????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[14 : 10]; // @ Misc.scala l254
      end
      32'b00000000000101000??????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[14 : 10]; // @ Misc.scala l254
      end
      32'b00000000000101001??????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[14 : 10]; // @ Misc.scala l254
      end
      32'b00000000000101010??????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[14 : 10]; // @ Misc.scala l254
      end
      32'b00000000000101011??????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[14 : 10]; // @ Misc.scala l254
      end
      32'b00000000000101110??????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[14 : 10]; // @ Misc.scala l254
      end
      32'b00000000000101111??????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[14 : 10]; // @ Misc.scala l254
      end
      32'b00000000000110000??????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[14 : 10]; // @ Misc.scala l254
      end
      32'b00000000000100100??????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[14 : 10]; // @ Misc.scala l254
      end
      32'b00000000000100101??????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[14 : 10]; // @ Misc.scala l254
      end
      32'b010110?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b010111?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b011000?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b011010?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b011001?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b011011?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b0010100100?????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b0010100110?????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b0010100101?????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00100001???????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_rs2_addr = 5'h00; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_rs2_addr = tmp_decode_DecodePlugin_rs2_addr; // @ DecodePlugin.scala l262
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b00000000000100000??????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000100010??????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101000??????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101001??????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101010??????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101011??????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101110??????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101111??????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000110000??????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000100100??????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000100101??????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b010110?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b010111?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b011000?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b011010?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b011001?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b011011?????????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b0010100100?????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b0010100101?????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b0010100110?????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b00100001???????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b1; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_rs2_req = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_rs2_req = tmp_decode_DecodePlugin_rs2_req; // @ DecodePlugin.scala l288
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b0000001110?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b0000001101?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b0000001111?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000000000100000??????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b0000001010?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000000000100010??????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000000000101000??????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000000000101001??????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000000000101010??????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000000000101011??????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000000000101110??????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000000000101111??????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000000000110000??????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000000010000001??????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000000010001001??????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000000010010001??????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000000000100100??????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000000000100101??????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b010011?????????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b0001010????????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b0001110????????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b010101?????????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = 5'h01; // @ Misc.scala l254
      end
      32'b0010100000?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b0010100001?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b0010101001?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b0010101000?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b0010100010?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00100000???????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_rd_addr = decode_INSTRUCTION[4 : 0]; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_rd_addr = 5'h00; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_rd_addr = tmp_decode_DecodePlugin_rd_addr; // @ DecodePlugin.scala l314
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b0000001110?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b0000001101?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b0000001111?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000100000??????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b0000001010?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000100010??????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101000??????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101001??????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101010??????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101011??????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101110??????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000101111??????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000110000??????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000000010000001??????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000000010001001??????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000000010010001??????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000100100??????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000000000100101??????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b010011?????????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b0001010????????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b0001110????????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b010101?????????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b0010100000?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b0010100001?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b0010101001?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b0010101000?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b0010100010?????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00100000???????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b1; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_rd_wen = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_rd_wen = tmp_decode_DecodePlugin_rd_wen; // @ DecodePlugin.scala l349
  assign decode_DecodePlugin_rs1 = regFileModule_1_read_ports_rs1_value; // @ DecodePlugin.scala l390
  assign decode_DecodePlugin_rs2 = regFileModule_1_read_ports_rs2_value; // @ DecodePlugin.scala l391
  always @(*) begin
    if(decode_RS1_FROM_EX) begin
      tmp_decode_RS1 = tmp_execute_to_memaccess_ALU_RESULT; // @ DecodePlugin.scala l405
    end else begin
      if(decode_RS1_FROM_MEM) begin
        tmp_decode_RS1 = tmp_memaccess_to_writeback_RD; // @ DecodePlugin.scala l407
      end else begin
        if(decode_DecodePlugin_rs1_req) begin
          tmp_decode_RS1 = (decode_DecodePlugin_is_store ? tmp_tmp_decode_RS1 : decode_DecodePlugin_rs1); // @ DecodePlugin.scala l409
        end else begin
          tmp_decode_RS1 = decode_DecodePlugin_imm; // @ DecodePlugin.scala l411
        end
      end
    end
  end

  always @(*) begin
    if(decode_RS2_FROM_EX) begin
      tmp_decode_RS2 = tmp_execute_to_memaccess_ALU_RESULT; // @ DecodePlugin.scala l415
    end else begin
      if(decode_RS2_FROM_MEM) begin
        tmp_decode_RS2 = tmp_memaccess_to_writeback_RD; // @ DecodePlugin.scala l417
      end else begin
        if(decode_DecodePlugin_rs2_req) begin
          tmp_decode_RS2 = decode_DecodePlugin_rs2; // @ DecodePlugin.scala l419
        end else begin
          tmp_decode_RS2 = decode_DecodePlugin_imm; // @ DecodePlugin.scala l421
        end
      end
    end
  end

  assign decode_DecodePlugin_rs1_eq_rs2 = ($signed(tmp_decode_DecodePlugin_rs1_eq_rs2) == $signed(tmp_decode_DecodePlugin_rs1_eq_rs2_1)); // @ DecodePlugin.scala l424
  assign decode_DecodePlugin_rs1_ne_rs2 = ($signed(tmp_decode_DecodePlugin_rs1_ne_rs2) != $signed(tmp_decode_DecodePlugin_rs1_ne_rs2_1)); // @ DecodePlugin.scala l425
  assign decode_DecodePlugin_rs1_lt_rs2 = ($signed(tmp_decode_DecodePlugin_rs1_lt_rs2) < $signed(tmp_decode_DecodePlugin_rs1_lt_rs2_1)); // @ DecodePlugin.scala l426
  assign decode_DecodePlugin_rs1_ltu_rs2 = (decode_RS1 < decode_RS2); // @ DecodePlugin.scala l427
  assign decode_DecodePlugin_rs1_ge_rs2 = ($signed(tmp_decode_DecodePlugin_rs1_ge_rs2) <= $signed(tmp_decode_DecodePlugin_rs1_ge_rs2_1)); // @ DecodePlugin.scala l428
  assign decode_DecodePlugin_rs1_geu_rs2 = (decode_RS2 <= decode_RS1); // @ DecodePlugin.scala l429
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b010011?????????????????????????? : begin
        tmp_decode_DecodePlugin_link_addr = tmp_tmp_decode_DecodePlugin_link_addr; // @ Misc.scala l254
      end
      32'b010101?????????????????????????? : begin
        tmp_decode_DecodePlugin_link_addr = tmp_tmp_decode_DecodePlugin_link_addr_2; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_link_addr = 32'h00000000; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_link_addr = tmp_decode_DecodePlugin_link_addr; // @ DecodePlugin.scala l431
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b010110?????????????????????????? : begin
        tmp_decode_DecodePlugin_fetch_dec_branch = decode_DecodePlugin_rs1_eq_rs2; // @ Misc.scala l254
      end
      32'b010111?????????????????????????? : begin
        tmp_decode_DecodePlugin_fetch_dec_branch = decode_DecodePlugin_rs1_ne_rs2; // @ Misc.scala l254
      end
      32'b011000?????????????????????????? : begin
        tmp_decode_DecodePlugin_fetch_dec_branch = decode_DecodePlugin_rs1_lt_rs2; // @ Misc.scala l254
      end
      32'b011010?????????????????????????? : begin
        tmp_decode_DecodePlugin_fetch_dec_branch = decode_DecodePlugin_rs1_ltu_rs2; // @ Misc.scala l254
      end
      32'b011001?????????????????????????? : begin
        tmp_decode_DecodePlugin_fetch_dec_branch = decode_DecodePlugin_rs1_ge_rs2; // @ Misc.scala l254
      end
      32'b011011?????????????????????????? : begin
        tmp_decode_DecodePlugin_fetch_dec_branch = decode_DecodePlugin_rs1_geu_rs2; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_fetch_dec_branch = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_fetch_dec_branch = tmp_decode_DecodePlugin_fetch_dec_branch; // @ DecodePlugin.scala l437
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b010011?????????????????????????? : begin
        tmp_decode_DecodePlugin_pc_next = tmp_tmp_decode_DecodePlugin_pc_next; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_pc_next = tmp_tmp_decode_DecodePlugin_pc_next_3; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_pc_next = tmp_decode_DecodePlugin_pc_next; // @ DecodePlugin.scala l447
  assign decode_DecodePlugin_is_jirl = (((decode_INSTRUCTION & 32'hfc000000) == 32'h4c000000) ? 1'b1 : 1'b0); // @ DecodePlugin.scala l452
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b010110?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_branch = 1'b1; // @ Misc.scala l254
      end
      32'b010111?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_branch = 1'b1; // @ Misc.scala l254
      end
      32'b011000?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_branch = 1'b1; // @ Misc.scala l254
      end
      32'b011010?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_branch = 1'b1; // @ Misc.scala l254
      end
      32'b011001?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_branch = 1'b1; // @ Misc.scala l254
      end
      32'b011011?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_branch = 1'b1; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_is_branch = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_is_branch = tmp_decode_DecodePlugin_is_branch; // @ DecodePlugin.scala l453
  assign decode_DecodePlugin_is_bl = (((decode_INSTRUCTION & 32'hfc000000) == 32'h54000000) ? 1'b1 : 1'b0); // @ DecodePlugin.scala l462
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b0010100000?????????????????????? : begin
        tmp_decode_DecodePlugin_mem_ctrl = MemCtrlEnum_LD_B; // @ Misc.scala l254
      end
      32'b0010100001?????????????????????? : begin
        tmp_decode_DecodePlugin_mem_ctrl = MemCtrlEnum_LD_H; // @ Misc.scala l254
      end
      32'b0010100010?????????????????????? : begin
        tmp_decode_DecodePlugin_mem_ctrl = MemCtrlEnum_LD_W; // @ Misc.scala l254
      end
      32'b0010101000?????????????????????? : begin
        tmp_decode_DecodePlugin_mem_ctrl = MemCtrlEnum_LD_BU; // @ Misc.scala l254
      end
      32'b0010101001?????????????????????? : begin
        tmp_decode_DecodePlugin_mem_ctrl = MemCtrlEnum_LD_HU; // @ Misc.scala l254
      end
      32'b0010100100?????????????????????? : begin
        tmp_decode_DecodePlugin_mem_ctrl = MemCtrlEnum_ST_B; // @ Misc.scala l254
      end
      32'b0010100101?????????????????????? : begin
        tmp_decode_DecodePlugin_mem_ctrl = MemCtrlEnum_ST_H; // @ Misc.scala l254
      end
      32'b0010100110?????????????????????? : begin
        tmp_decode_DecodePlugin_mem_ctrl = MemCtrlEnum_ST_W; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_mem_ctrl = 4'b0000; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_mem_ctrl = tmp_decode_DecodePlugin_mem_ctrl; // @ DecodePlugin.scala l517
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b0010100100?????????????????????? : begin
        tmp_decode_DecodePlugin_mem_wdata = decode_DecodePlugin_rs2; // @ Misc.scala l254
      end
      32'b0010100101?????????????????????? : begin
        tmp_decode_DecodePlugin_mem_wdata = decode_DecodePlugin_rs2; // @ Misc.scala l254
      end
      32'b0010100110?????????????????????? : begin
        tmp_decode_DecodePlugin_mem_wdata = decode_DecodePlugin_rs2; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_mem_wdata = 32'h00000000; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_mem_wdata = tmp_decode_DecodePlugin_mem_wdata; // @ DecodePlugin.scala l529
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b0010100000?????????????????????? : begin
        tmp_decode_DecodePlugin_is_load = 1'b1; // @ Misc.scala l254
      end
      32'b0010100001?????????????????????? : begin
        tmp_decode_DecodePlugin_is_load = 1'b1; // @ Misc.scala l254
      end
      32'b0010100010?????????????????????? : begin
        tmp_decode_DecodePlugin_is_load = 1'b1; // @ Misc.scala l254
      end
      32'b0010101000?????????????????????? : begin
        tmp_decode_DecodePlugin_is_load = 1'b1; // @ Misc.scala l254
      end
      32'b0010101001?????????????????????? : begin
        tmp_decode_DecodePlugin_is_load = 1'b1; // @ Misc.scala l254
      end
      32'b00100000???????????????????????? : begin
        tmp_decode_DecodePlugin_is_load = 1'b1; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_is_load = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_is_load = tmp_decode_DecodePlugin_is_load; // @ DecodePlugin.scala l536
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b0010100100?????????????????????? : begin
        tmp_decode_DecodePlugin_is_store = 1'b1; // @ Misc.scala l254
      end
      32'b0010100101?????????????????????? : begin
        tmp_decode_DecodePlugin_is_store = 1'b1; // @ Misc.scala l254
      end
      32'b0010100110?????????????????????? : begin
        tmp_decode_DecodePlugin_is_store = 1'b1; // @ Misc.scala l254
      end
      32'b00100001???????????????????????? : begin
        tmp_decode_DecodePlugin_is_store = 1'b1; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_is_store = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_is_store = tmp_decode_DecodePlugin_is_store; // @ DecodePlugin.scala l546
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b0000001110?????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b0000001101?????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b0000001111?????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000000100000??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b0000001010?????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000000100010??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000000101000??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000000101001??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000000101010??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000000101011??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000000101110??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000000101111??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000000110000??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000010000001??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000010001001??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000010010001??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000000100100??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000000100101??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b010011?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b0001010????????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b0001110????????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b010110?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b010111?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b011000?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b011010?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b011001?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b011011?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b0010100000?????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b0010101000?????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b0010100001?????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b0010101001?????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b0010100010?????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b0010100100?????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b0010100110?????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b0010100101?????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00100000???????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00100001???????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b0000011001001000001110?????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000001010100??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b00000000001010110??????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b010100?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      32'b010101?????????????????????????? : begin
        tmp_decode_DecodePlugin_is_ine = 1'b0; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_is_ine = 1'b1; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_is_ine = tmp_decode_DecodePlugin_is_ine; // @ DecodePlugin.scala l559
  always @(*) begin
    case(tmp_8)
      5'h00 : begin
        tmp_decode_DecodePlugin_csr_ctrl = CsrCtrlEnum_CSRRD; // @ Misc.scala l254
      end
      5'h01 : begin
        tmp_decode_DecodePlugin_csr_ctrl = CsrCtrlEnum_CSRWR; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_csr_ctrl = CsrCtrlEnum_CSRXCHG; // @ Misc.scala l250
      end
    endcase
  end

  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_csr_ctrl_1 = tmp_decode_DecodePlugin_csr_ctrl; // @ Misc.scala l254
      end
      32'b0000011001001000001110?????????? : begin
        tmp_decode_DecodePlugin_csr_ctrl_1 = CsrCtrlEnum_ERTN; // @ Misc.scala l254
      end
      32'b00000000001010110??????????????? : begin
        tmp_decode_DecodePlugin_csr_ctrl_1 = CsrCtrlEnum_SYSCALL; // @ Misc.scala l254
      end
      32'b00000000001010100??????????????? : begin
        tmp_decode_DecodePlugin_csr_ctrl_1 = CsrCtrlEnum_BREAK_1; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_csr_ctrl_1 = 4'b0000; // @ Misc.scala l250
      end
    endcase
  end

  always @(*) begin
    if((! decode_DecodePlugin_is_adef)) begin
      if((! decode_DecodePlugin_is_ine)) begin
        decode_DecodePlugin_csr_ctrl = tmp_decode_DecodePlugin_csr_ctrl_1; // @ DecodePlugin.scala l610
      end else begin
        decode_DecodePlugin_csr_ctrl = CsrCtrlEnum_INE; // @ DecodePlugin.scala l621
      end
    end else begin
      decode_DecodePlugin_csr_ctrl = CsrCtrlEnum_ADEF; // @ DecodePlugin.scala l624
    end
  end

  assign decode_DecodePlugin_csr_addr = decode_INSTRUCTION[23 : 10]; // @ DecodePlugin.scala l627
  always @(*) begin
    case(tmp_9)
      5'h00 : begin
        tmp_decode_DecodePlugin_csr_wen = 1'b0; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_csr_wen = 1'b1; // @ Misc.scala l250
      end
    endcase
  end

  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_csr_wen_1 = tmp_decode_DecodePlugin_csr_wen; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_csr_wen_1 = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_csr_wen = tmp_decode_DecodePlugin_csr_wen_1; // @ DecodePlugin.scala l629
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b00000100???????????????????????? : begin
        tmp_decode_DecodePlugin_is_csr = 1'b1; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_is_csr = 1'b0; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_is_csr = tmp_decode_DecodePlugin_is_csr; // @ DecodePlugin.scala l636
  always @(*) begin
    casez(decode_INSTRUCTION)
      32'b00000000001010110??????????????? : begin
        tmp_decode_DecodePlugin_csr_code = decode_INSTRUCTION[14 : 0]; // @ Misc.scala l254
      end
      default : begin
        tmp_decode_DecodePlugin_csr_code = 15'h0000; // @ Misc.scala l250
      end
    endcase
  end

  assign decode_DecodePlugin_csr_code = tmp_decode_DecodePlugin_csr_code; // @ DecodePlugin.scala l641
  assign regFileModule_1_write_ports_rd_wen = (writeback_arbitration_isFiring && writeback_RD_WEN); // @ DecodePlugin.scala l655
  assign execute_AluPlugin_sub_result = ($signed(tmp_execute_AluPlugin_sub_result) - $signed(tmp_execute_AluPlugin_sub_result_1)); // @ BaseType.scala l299
  assign execute_AluPlugin_shift_bits = execute_AluPlugin_src2[4 : 0]; // @ BaseType.scala l318
  assign execute_AluPlugin_sll_result = (execute_AluPlugin_src1 <<< execute_AluPlugin_shift_bits); // @ BaseType.scala l299
  assign execute_AluPlugin_srl_result = (execute_AluPlugin_src1 >>> execute_AluPlugin_shift_bits); // @ BaseType.scala l299
  assign execute_AluPlugin_sra_result = ($signed(tmp_execute_AluPlugin_sra_result) >>> execute_AluPlugin_shift_bits); // @ BaseType.scala l299
  assign execute_AluPlugin_or_result = (execute_AluPlugin_src1 | execute_AluPlugin_src2); // @ BaseType.scala l299
  assign execute_AluPlugin_and_result = (execute_AluPlugin_src1 & execute_AluPlugin_src2); // @ BaseType.scala l299
  assign execute_AluPlugin_xor_result = (execute_AluPlugin_src1 ^ execute_AluPlugin_src2); // @ BaseType.scala l299
  assign execute_AluPlugin_nor_result = (~ (execute_AluPlugin_src1 | execute_AluPlugin_src2)); // @ BaseType.scala l299
  assign execute_AluPlugin_add_result = ($signed(tmp_execute_AluPlugin_add_result) + $signed(tmp_execute_AluPlugin_add_result_1)); // @ BaseType.scala l299
  assign execute_AluPlugin_slt_result = ($signed(tmp_execute_AluPlugin_slt_result) < $signed(tmp_execute_AluPlugin_slt_result_1)); // @ BaseType.scala l305
  assign execute_AluPlugin_sltu_result = (execute_AluPlugin_src1 < execute_AluPlugin_src2); // @ BaseType.scala l305
  assign execute_AluPlugin_src1 = execute_RS1; // @ AluPlugin.scala l37
  assign execute_AluPlugin_src2 = execute_RS2; // @ AluPlugin.scala l38
  always @(*) begin
    if((execute_ALU_CTRL == AluCtrlEnum_OR_1)) begin
        tmp_execute_AluPlugin_alu_result = execute_AluPlugin_or_result; // @ Misc.scala l254
    end else if((execute_ALU_CTRL == AluCtrlEnum_AND_1)) begin
        tmp_execute_AluPlugin_alu_result = execute_AluPlugin_and_result; // @ Misc.scala l254
    end else if((execute_ALU_CTRL == AluCtrlEnum_XOR_1)) begin
        tmp_execute_AluPlugin_alu_result = execute_AluPlugin_xor_result; // @ Misc.scala l254
    end else if((execute_ALU_CTRL == AluCtrlEnum_ADD)) begin
        tmp_execute_AluPlugin_alu_result = execute_AluPlugin_add_result; // @ Misc.scala l254
    end else if((execute_ALU_CTRL == AluCtrlEnum_SUB)) begin
        tmp_execute_AluPlugin_alu_result = execute_AluPlugin_sub_result; // @ Misc.scala l254
    end else if((execute_ALU_CTRL == AluCtrlEnum_SLL_1)) begin
        tmp_execute_AluPlugin_alu_result = execute_AluPlugin_sll_result; // @ Misc.scala l254
    end else if((execute_ALU_CTRL == AluCtrlEnum_SRL_1)) begin
        tmp_execute_AluPlugin_alu_result = execute_AluPlugin_srl_result; // @ Misc.scala l254
    end else if((execute_ALU_CTRL == AluCtrlEnum_SRA_1)) begin
        tmp_execute_AluPlugin_alu_result = execute_AluPlugin_sra_result; // @ Misc.scala l254
    end else if((execute_ALU_CTRL == AluCtrlEnum_NOR_1)) begin
        tmp_execute_AluPlugin_alu_result = execute_AluPlugin_nor_result; // @ Misc.scala l254
    end else if((execute_ALU_CTRL == AluCtrlEnum_SLT)) begin
        tmp_execute_AluPlugin_alu_result = {31'h00000000,execute_AluPlugin_slt_result}; // @ Misc.scala l254
    end else if((execute_ALU_CTRL == AluCtrlEnum_SLTU)) begin
        tmp_execute_AluPlugin_alu_result = {31'h00000000,execute_AluPlugin_sltu_result}; // @ Misc.scala l254
    end else if((execute_ALU_CTRL == AluCtrlEnum_JIRL)) begin
        tmp_execute_AluPlugin_alu_result = execute_LINK_ADDR; // @ Misc.scala l254
    end else if((execute_ALU_CTRL == AluCtrlEnum_BL)) begin
        tmp_execute_AluPlugin_alu_result = execute_LINK_ADDR; // @ Misc.scala l254
    end else begin
        tmp_execute_AluPlugin_alu_result = 32'h00000000; // @ Misc.scala l250
    end
  end

  assign execute_AluPlugin_alu_result = tmp_execute_AluPlugin_alu_result; // @ AluPlugin.scala l39
  assign DecodePlugin_hazard_rs1_from_mem = (((memaccess_arbitration_isValid && tmp_DecodePlugin_hazard_rs1_from_mem_1) && (tmp_DecodePlugin_hazard_rs1_from_mem == decode_RS1_ADDR)) && decode_RS1_REQ); // @ ControlPlugin.scala l45
  assign DecodePlugin_hazard_rs2_from_mem = (((memaccess_arbitration_isValid && tmp_DecodePlugin_hazard_rs1_from_mem_1) && (tmp_DecodePlugin_hazard_rs1_from_mem == decode_RS2_ADDR)) && decode_RS2_REQ); // @ ControlPlugin.scala l46
  assign DecodePlugin_hazard_rs1_from_ex = (((execute_arbitration_isValid && tmp_DecodePlugin_hazard_rs1_from_ex_1) && (tmp_DecodePlugin_hazard_rs1_from_ex == decode_RS1_ADDR)) && decode_RS1_REQ); // @ ControlPlugin.scala l47
  assign DecodePlugin_hazard_rs2_from_ex = (((execute_arbitration_isValid && tmp_DecodePlugin_hazard_rs1_from_ex_1) && (tmp_DecodePlugin_hazard_rs1_from_ex == decode_RS2_ADDR)) && decode_RS2_REQ); // @ ControlPlugin.scala l48
  assign DecodePlugin_hazard_rs1_load_hit = ((tmp_DecodePlugin_hazard_rs1_from_ex == decode_RS1_ADDR) && decode_RS1_REQ); // @ ControlPlugin.scala l49
  assign DecodePlugin_hazard_rs2_load_hit = ((tmp_DecodePlugin_hazard_rs1_from_ex == decode_RS2_ADDR) && decode_RS2_REQ); // @ ControlPlugin.scala l50
  assign fetch_arbitration_haltItself = 1'b0; // @ ControlPlugin.scala l55
  assign fetch_arbitration_flushIt = ((tmp_fetch_arbitration_flushIt_2 || tmp_fetch_arbitration_flushIt_1) || tmp_fetch_arbitration_flushIt); // @ ControlPlugin.scala l56
  assign decode_arbitration_haltItself = (execute_IS_LOAD && (DecodePlugin_hazard_rs1_load_hit || DecodePlugin_hazard_rs2_load_hit)); // @ ControlPlugin.scala l66
  assign decode_arbitration_flushIt = (tmp_fetch_arbitration_flushIt_1 || tmp_fetch_arbitration_flushIt); // @ ControlPlugin.scala l67
  assign execute_arbitration_haltItself = 1'b0; // @ ControlPlugin.scala l73
  assign execute_arbitration_flushIt = tmp_fetch_arbitration_flushIt; // @ ControlPlugin.scala l74
  assign memaccess_arbitration_haltItself = tmp_memaccess_arbitration_haltItself; // @ ControlPlugin.scala l80
  assign memaccess_arbitration_flushIt = tmp_fetch_arbitration_flushIt; // @ ControlPlugin.scala l81
  assign writeback_arbitration_haltItself = tmp_memaccess_arbitration_haltItself; // @ ControlPlugin.scala l87
  assign writeback_arbitration_flushIt = 1'b0; // @ ControlPlugin.scala l88
  assign csrRegfile_1_cpu_ports_raddr = decode_CSR_ADDR; // @ ExcepPlugin.scala l177
  assign execute_ExcepPlugin_csrxchg_wdata = ((execute_RS1 & execute_RS2) | ((~ execute_RS2) & execute_CSR_RDATA)); // @ BaseType.scala l299
  assign execute_ExcepPlugin_is_ertn = (execute_CSR_CTRL == CsrCtrlEnum_ERTN); // @ BaseType.scala l305
  assign execute_ExcepPlugin_is_syscall = (execute_CSR_CTRL == CsrCtrlEnum_SYSCALL); // @ BaseType.scala l305
  assign execute_ExcepPlugin_is_break = (execute_CSR_CTRL == CsrCtrlEnum_BREAK_1); // @ BaseType.scala l305
  assign execute_ExcepPlugin_is_adef = (execute_CSR_CTRL == CsrCtrlEnum_ADEF); // @ BaseType.scala l305
  assign execute_ExcepPlugin_is_ine = (execute_CSR_CTRL == CsrCtrlEnum_INE); // @ BaseType.scala l305
  always @(*) begin
    if((execute_CSR_CTRL == CsrCtrlEnum_CSRWR)) begin
        tmp_execute_ExcepPlugin_csr_wdata = execute_RS1; // @ Misc.scala l254
    end else if((execute_CSR_CTRL == CsrCtrlEnum_CSRXCHG)) begin
        tmp_execute_ExcepPlugin_csr_wdata = execute_ExcepPlugin_csrxchg_wdata; // @ Misc.scala l254
    end else begin
        tmp_execute_ExcepPlugin_csr_wdata = 32'h00000000; // @ Misc.scala l250
    end
  end

  assign execute_ExcepPlugin_csr_wdata = tmp_execute_ExcepPlugin_csr_wdata; // @ ExcepPlugin.scala l194
  assign csrRegfile_1_cpu_ports_pc = execute_PC; // @ ExcepPlugin.scala l200
  assign csrRegfile_1_cpu_ports_waddr = execute_CSR_ADDR; // @ ExcepPlugin.scala l207
  assign memaccess_LsuPlugin_cpu_addr = memaccess_ALU_RESULT; // @ BaseType.scala l318
  assign memaccess_LsuPlugin_is_mem = (memaccess_IS_STORE || memaccess_IS_LOAD); // @ BaseType.scala l305
  assign memaccess_LsuPlugin_cpu_addr_sel = memaccess_LsuPlugin_cpu_addr[1 : 0]; // @ BaseType.scala l299
  assign memaccess_LsuPlugin_dcache_rdata = (DCachePlugin_dcache_access_rsp_payload_data >>> tmp_memaccess_LsuPlugin_dcache_rdata); // @ BaseType.scala l299
  assign tmp_memaccess_LsuPlugin_dcache_ld_b = memaccess_LsuPlugin_dcache_rdata[7]; // @ BaseType.scala l305
  always @(*) begin
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[23] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[22] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[21] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[20] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[19] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[18] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[17] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[16] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[15] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[14] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[13] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[12] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[11] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[10] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[9] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[8] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[7] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[6] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[5] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[4] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[3] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[2] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[1] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_b_1[0] = tmp_memaccess_LsuPlugin_dcache_ld_b; // @ Literal.scala l87
  end

  assign memaccess_LsuPlugin_dcache_ld_b = {tmp_memaccess_LsuPlugin_dcache_ld_b_1,memaccess_LsuPlugin_dcache_rdata[7 : 0]}; // @ BaseType.scala l299
  assign tmp_12 = zz_tmp_memaccess_LsuPlugin_dcache_ld_bu(1'b0);
  always @(*) tmp_memaccess_LsuPlugin_dcache_ld_bu = tmp_12;
  assign memaccess_LsuPlugin_dcache_ld_bu = {tmp_memaccess_LsuPlugin_dcache_ld_bu,memaccess_LsuPlugin_dcache_rdata[7 : 0]}; // @ BaseType.scala l299
  assign tmp_memaccess_LsuPlugin_dcache_ld_h = memaccess_LsuPlugin_dcache_rdata[15]; // @ BaseType.scala l305
  always @(*) begin
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[15] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[14] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[13] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[12] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[11] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[10] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[9] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[8] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[7] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[6] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[5] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[4] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[3] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[2] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[1] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_ld_h_1[0] = tmp_memaccess_LsuPlugin_dcache_ld_h; // @ Literal.scala l87
  end

  assign memaccess_LsuPlugin_dcache_ld_h = {tmp_memaccess_LsuPlugin_dcache_ld_h_1,memaccess_LsuPlugin_dcache_rdata[15 : 0]}; // @ BaseType.scala l299
  assign tmp_13 = zz_tmp_memaccess_LsuPlugin_dcache_ld_hu(1'b0);
  always @(*) tmp_memaccess_LsuPlugin_dcache_ld_hu = tmp_13;
  assign memaccess_LsuPlugin_dcache_ld_hu = {tmp_memaccess_LsuPlugin_dcache_ld_hu,memaccess_LsuPlugin_dcache_rdata[15 : 0]}; // @ BaseType.scala l299
  assign memaccess_LsuPlugin_dcache_ld_w = memaccess_LsuPlugin_dcache_rdata[31 : 0]; // @ BaseType.scala l299
  assign tmp_memaccess_LsuPlugin_dcache_st_b = memaccess_MEM_WDATA[7]; // @ BaseType.scala l305
  always @(*) begin
    tmp_memaccess_LsuPlugin_dcache_st_b_1[23] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[22] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[21] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[20] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[19] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[18] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[17] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[16] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[15] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[14] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[13] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[12] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[11] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[10] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[9] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[8] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[7] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[6] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[5] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[4] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[3] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[2] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[1] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_b_1[0] = tmp_memaccess_LsuPlugin_dcache_st_b; // @ Literal.scala l87
  end

  assign memaccess_LsuPlugin_dcache_st_b = {tmp_memaccess_LsuPlugin_dcache_st_b_1,memaccess_MEM_WDATA[7 : 0]}; // @ BaseType.scala l299
  assign tmp_memaccess_LsuPlugin_dcache_st_h = memaccess_MEM_WDATA[15]; // @ BaseType.scala l305
  always @(*) begin
    tmp_memaccess_LsuPlugin_dcache_st_h_1[15] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[14] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[13] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[12] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[11] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[10] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[9] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[8] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[7] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[6] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[5] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[4] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[3] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[2] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[1] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
    tmp_memaccess_LsuPlugin_dcache_st_h_1[0] = tmp_memaccess_LsuPlugin_dcache_st_h; // @ Literal.scala l87
  end

  assign memaccess_LsuPlugin_dcache_st_h = {tmp_memaccess_LsuPlugin_dcache_st_h_1,memaccess_MEM_WDATA[15 : 0]}; // @ BaseType.scala l299
  assign memaccess_LsuPlugin_dcache_st_w = memaccess_MEM_WDATA[31 : 0]; // @ BaseType.scala l299
  always @(*) begin
    memaccess_LsuPlugin_LLbit_data = 1'b0; // @ LsuPlugin.scala l85
    if(memaccess_LsuPlugin_is_sc) begin
      if(!tmp_when_5) begin
        memaccess_LsuPlugin_LLbit_data = 1'b0; // @ LsuPlugin.scala l94
      end
    end
    if(memaccess_LsuPlugin_is_ll) begin
      memaccess_LsuPlugin_LLbit_data = 1'b1; // @ LsuPlugin.scala l100
    end
  end

  always @(*) begin
    memaccess_LsuPlugin_LLbit_we = 1'b0; // @ LsuPlugin.scala l86
    if(memaccess_LsuPlugin_is_sc) begin
      if(!tmp_when_5) begin
        memaccess_LsuPlugin_LLbit_we = 1'b1; // @ LsuPlugin.scala l95
      end
    end
    if(memaccess_LsuPlugin_is_ll) begin
      memaccess_LsuPlugin_LLbit_we = 1'b0; // @ LsuPlugin.scala l101
    end
  end

  assign memaccess_LsuPlugin_is_sc = (memaccess_MEM_CTRL == MemCtrlEnum_LL); // @ BaseType.scala l305
  assign memaccess_LsuPlugin_is_ll = (memaccess_MEM_CTRL == MemCtrlEnum_SC); // @ BaseType.scala l305
  always @(*) begin
    if((memaccess_MEM_CTRL == MemCtrlEnum_LD_H)) begin
        tmp_memaccess_LsuPlugin_is_ale = (tmp_tmp_memaccess_LsuPlugin_is_ale[0] != 1'b0); // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_LD_HU)) begin
        tmp_memaccess_LsuPlugin_is_ale = (tmp_tmp_memaccess_LsuPlugin_is_ale_1[0] != 1'b0); // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_LD_W)) begin
        tmp_memaccess_LsuPlugin_is_ale = (tmp_tmp_memaccess_LsuPlugin_is_ale_2[1 : 0] != 2'b00); // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_LL)) begin
        tmp_memaccess_LsuPlugin_is_ale = (tmp_tmp_memaccess_LsuPlugin_is_ale_3[1 : 0] != 2'b00); // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_ST_H)) begin
        tmp_memaccess_LsuPlugin_is_ale = (tmp_tmp_memaccess_LsuPlugin_is_ale_4[0] != 1'b0); // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_ST_W)) begin
        tmp_memaccess_LsuPlugin_is_ale = (tmp_tmp_memaccess_LsuPlugin_is_ale_5[1 : 0] != 2'b00); // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_SC)) begin
        tmp_memaccess_LsuPlugin_is_ale = (tmp_tmp_memaccess_LsuPlugin_is_ale_6[1 : 0] != 2'b00); // @ Misc.scala l254
    end else begin
        tmp_memaccess_LsuPlugin_is_ale = 1'b0; // @ Misc.scala l250
    end
  end

  assign memaccess_LsuPlugin_is_ale = tmp_memaccess_LsuPlugin_is_ale; // @ LsuPlugin.scala l104
  always @(*) begin
    if((memaccess_MEM_CTRL == MemCtrlEnum_LD_B)) begin
        tmp_memaccess_LsuPlugin_dcache_data_load = memaccess_LsuPlugin_dcache_ld_b; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_LD_BU)) begin
        tmp_memaccess_LsuPlugin_dcache_data_load = memaccess_LsuPlugin_dcache_ld_bu; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_LD_H)) begin
        tmp_memaccess_LsuPlugin_dcache_data_load = memaccess_LsuPlugin_dcache_ld_h; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_LD_HU)) begin
        tmp_memaccess_LsuPlugin_dcache_data_load = memaccess_LsuPlugin_dcache_ld_hu; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_LD_W)) begin
        tmp_memaccess_LsuPlugin_dcache_data_load = memaccess_LsuPlugin_dcache_ld_w; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_LL)) begin
        tmp_memaccess_LsuPlugin_dcache_data_load = memaccess_LsuPlugin_dcache_ld_w; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_ST_B)) begin
        tmp_memaccess_LsuPlugin_dcache_data_load = memaccess_LsuPlugin_dcache_st_b; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_ST_H)) begin
        tmp_memaccess_LsuPlugin_dcache_data_load = memaccess_LsuPlugin_dcache_st_h; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_ST_W)) begin
        tmp_memaccess_LsuPlugin_dcache_data_load = memaccess_LsuPlugin_dcache_st_w; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_SC)) begin
        tmp_memaccess_LsuPlugin_dcache_data_load = memaccess_LsuPlugin_dcache_st_w; // @ Misc.scala l254
    end else begin
        tmp_memaccess_LsuPlugin_dcache_data_load = 32'h00000000; // @ Misc.scala l250
    end
  end

  assign memaccess_LsuPlugin_dcache_data_load = tmp_memaccess_LsuPlugin_dcache_data_load; // @ LsuPlugin.scala l117
  always @(*) begin
    if((memaccess_MEM_CTRL == MemCtrlEnum_LD_B)) begin
        tmp_memaccess_LsuPlugin_lsu_size = 2'b00; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_LD_BU)) begin
        tmp_memaccess_LsuPlugin_lsu_size = 2'b00; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_LD_H)) begin
        tmp_memaccess_LsuPlugin_lsu_size = 2'b01; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_LD_HU)) begin
        tmp_memaccess_LsuPlugin_lsu_size = 2'b01; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_LD_W)) begin
        tmp_memaccess_LsuPlugin_lsu_size = 2'b10; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_LL)) begin
        tmp_memaccess_LsuPlugin_lsu_size = 2'b10; // @ Misc.scala l254
    end else begin
        tmp_memaccess_LsuPlugin_lsu_size = 2'b00; // @ Misc.scala l250
    end
  end

  assign memaccess_LsuPlugin_lsu_size = tmp_memaccess_LsuPlugin_lsu_size; // @ LsuPlugin.scala l131
  always @(*) begin
    if((memaccess_MEM_CTRL == MemCtrlEnum_ST_B)) begin
        tmp_memaccess_LsuPlugin_dcache_wdata = memaccess_LsuPlugin_dcache_st_b; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_ST_H)) begin
        tmp_memaccess_LsuPlugin_dcache_wdata = memaccess_LsuPlugin_dcache_st_h; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_ST_W)) begin
        tmp_memaccess_LsuPlugin_dcache_wdata = memaccess_LsuPlugin_dcache_st_w; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_SC)) begin
        tmp_memaccess_LsuPlugin_dcache_wdata = memaccess_LsuPlugin_dcache_st_w; // @ Misc.scala l254
    end else begin
        tmp_memaccess_LsuPlugin_dcache_wdata = 32'h00000000; // @ Misc.scala l250
    end
  end

  assign memaccess_LsuPlugin_dcache_wdata = tmp_memaccess_LsuPlugin_dcache_wdata; // @ LsuPlugin.scala l141
  assign tmp_14 = zz_tmp_memaccess_LsuPlugin_dcache_wstrb(1'b0);
  always @(*) tmp_memaccess_LsuPlugin_dcache_wstrb = tmp_14;
  assign tmp_15 = zz_tmp_memaccess_LsuPlugin_dcache_wstrb_1(1'b0);
  always @(*) tmp_memaccess_LsuPlugin_dcache_wstrb_1 = tmp_15;
  assign tmp_16 = zz_tmp_memaccess_LsuPlugin_dcache_wstrb_2(1'b0);
  always @(*) tmp_memaccess_LsuPlugin_dcache_wstrb_2 = tmp_16;
  assign tmp_17 = zz_tmp_memaccess_LsuPlugin_dcache_wstrb_3(1'b0);
  always @(*) tmp_memaccess_LsuPlugin_dcache_wstrb_3 = tmp_17;
  always @(*) begin
    if((memaccess_MEM_CTRL == MemCtrlEnum_ST_B)) begin
        tmp_memaccess_LsuPlugin_dcache_wstrb_4 = tmp_memaccess_LsuPlugin_dcache_wstrb; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_ST_H)) begin
        tmp_memaccess_LsuPlugin_dcache_wstrb_4 = tmp_memaccess_LsuPlugin_dcache_wstrb_1; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_ST_W)) begin
        tmp_memaccess_LsuPlugin_dcache_wstrb_4 = tmp_memaccess_LsuPlugin_dcache_wstrb_2; // @ Misc.scala l254
    end else if((memaccess_MEM_CTRL == MemCtrlEnum_SC)) begin
        tmp_memaccess_LsuPlugin_dcache_wstrb_4 = tmp_memaccess_LsuPlugin_dcache_wstrb_3; // @ Misc.scala l254
    end else begin
        tmp_memaccess_LsuPlugin_dcache_wstrb_4 = 4'b0000; // @ Misc.scala l250
    end
  end

  assign memaccess_LsuPlugin_dcache_wstrb = tmp_memaccess_LsuPlugin_dcache_wstrb_4; // @ LsuPlugin.scala l149
  assign memaccess_LsuPlugin_lsu_rdata = memaccess_LsuPlugin_dcache_data_load; // @ LsuPlugin.scala l160
  assign memaccess_LsuPlugin_lsu_wdata = (memaccess_LsuPlugin_dcache_wdata <<< tmp_memaccess_LsuPlugin_lsu_wdata); // @ LsuPlugin.scala l161
  assign memaccess_LsuPlugin_lsu_addr = memaccess_LsuPlugin_cpu_addr; // @ LsuPlugin.scala l162
  assign memaccess_LsuPlugin_lsu_wen = memaccess_IS_STORE; // @ LsuPlugin.scala l163
  assign memaccess_LsuPlugin_lsu_wstrb = (memaccess_LsuPlugin_dcache_wstrb <<< memaccess_LsuPlugin_cpu_addr_sel); // @ LsuPlugin.scala l164
  assign DCachePlugin_dcache_access_cmd_valid = (memaccess_LsuPlugin_is_mem && memaccess_arbitration_isValid); // @ LsuPlugin.scala l171
  assign DCachePlugin_dcache_access_cmd_payload_addr = memaccess_LsuPlugin_lsu_addr; // @ LsuPlugin.scala l172
  assign DCachePlugin_dcache_access_cmd_payload_wen = memaccess_LsuPlugin_lsu_wen; // @ LsuPlugin.scala l173
  assign DCachePlugin_dcache_access_cmd_payload_wdata = memaccess_LsuPlugin_lsu_wdata; // @ LsuPlugin.scala l174
  assign DCachePlugin_dcache_access_cmd_payload_wstrb = memaccess_LsuPlugin_lsu_wstrb; // @ LsuPlugin.scala l175
  assign DCachePlugin_dcache_access_cmd_payload_size = memaccess_LsuPlugin_lsu_size; // @ LsuPlugin.scala l176
  assign icache_cmd_valid = ICachePlugin_icache_access_cmd_valid; // @ ICachePlugin.scala l174
  assign ICachePlugin_icache_access_cmd_ready = icache_cmd_ready; // @ ICachePlugin.scala l174
  assign icache_cmd_payload_addr = ICachePlugin_icache_access_cmd_payload_addr; // @ ICachePlugin.scala l174
  assign ICachePlugin_icache_access_rsp_valid = icache_rsp_valid; // @ ICachePlugin.scala l175
  assign ICachePlugin_icache_access_rsp_payload_data = icache_rsp_payload_data; // @ ICachePlugin.scala l175
  assign dcache_cmd_valid = DCachePlugin_dcache_access_cmd_valid; // @ DCachePlugin.scala l83
  assign DCachePlugin_dcache_access_cmd_ready = dcache_cmd_ready; // @ DCachePlugin.scala l83
  assign dcache_cmd_payload_addr = DCachePlugin_dcache_access_cmd_payload_addr; // @ DCachePlugin.scala l83
  assign dcache_cmd_payload_wen = DCachePlugin_dcache_access_cmd_payload_wen; // @ DCachePlugin.scala l83
  assign dcache_cmd_payload_wdata = DCachePlugin_dcache_access_cmd_payload_wdata; // @ DCachePlugin.scala l83
  assign dcache_cmd_payload_wstrb = DCachePlugin_dcache_access_cmd_payload_wstrb; // @ DCachePlugin.scala l83
  assign dcache_cmd_payload_size = DCachePlugin_dcache_access_cmd_payload_size; // @ DCachePlugin.scala l83
  assign DCachePlugin_dcache_access_rsp_valid = dcache_rsp_valid; // @ DCachePlugin.scala l84
  assign DCachePlugin_dcache_access_rsp_payload_data = dcache_rsp_payload_data; // @ DCachePlugin.scala l84
  assign DCachePlugin_dcache_access_stall = 1'b0; // @ DCachePlugin.scala l85
  assign fetch_arbitration_isFlushed = ((|{writeback_arbitration_flushNext,{memaccess_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}}) || (|{writeback_arbitration_flushIt,{memaccess_arbitration_flushIt,{execute_arbitration_flushIt,{decode_arbitration_flushIt,fetch_arbitration_flushIt}}}})); // @ Pipeline.scala l135
  assign decode_arbitration_isFlushed = ((|{writeback_arbitration_flushNext,{memaccess_arbitration_flushNext,execute_arbitration_flushNext}}) || (|{writeback_arbitration_flushIt,{memaccess_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}})); // @ Pipeline.scala l135
  assign execute_arbitration_isFlushed = ((|{writeback_arbitration_flushNext,memaccess_arbitration_flushNext}) || (|{writeback_arbitration_flushIt,{memaccess_arbitration_flushIt,execute_arbitration_flushIt}})); // @ Pipeline.scala l135
  assign memaccess_arbitration_isFlushed = ((|writeback_arbitration_flushNext) || (|{writeback_arbitration_flushIt,memaccess_arbitration_flushIt})); // @ Pipeline.scala l135
  assign writeback_arbitration_isFlushed = (1'b0 || (|writeback_arbitration_flushIt)); // @ Pipeline.scala l135
  assign fetch_arbitration_isStuckByOthers = (fetch_arbitration_haltByOther || ((((1'b0 || decode_arbitration_isStuck) || execute_arbitration_isStuck) || memaccess_arbitration_isStuck) || writeback_arbitration_isStuck)); // @ Pipeline.scala l144
  assign fetch_arbitration_isStuck = (fetch_arbitration_haltItself || fetch_arbitration_isStuckByOthers); // @ Pipeline.scala l145
  assign fetch_arbitration_isMoving = ((! fetch_arbitration_isStuck) && (! fetch_arbitration_removeIt)); // @ Pipeline.scala l146
  assign fetch_arbitration_isFiring = ((fetch_arbitration_isValid && (! fetch_arbitration_isStuck)) && (! fetch_arbitration_removeIt)); // @ Pipeline.scala l147
  assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memaccess_arbitration_isStuck) || writeback_arbitration_isStuck)); // @ Pipeline.scala l144
  assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); // @ Pipeline.scala l145
  assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); // @ Pipeline.scala l146
  assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); // @ Pipeline.scala l147
  assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memaccess_arbitration_isStuck) || writeback_arbitration_isStuck)); // @ Pipeline.scala l144
  assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); // @ Pipeline.scala l145
  assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); // @ Pipeline.scala l146
  assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); // @ Pipeline.scala l147
  assign memaccess_arbitration_isStuckByOthers = (memaccess_arbitration_haltByOther || (1'b0 || writeback_arbitration_isStuck)); // @ Pipeline.scala l144
  assign memaccess_arbitration_isStuck = (memaccess_arbitration_haltItself || memaccess_arbitration_isStuckByOthers); // @ Pipeline.scala l145
  assign memaccess_arbitration_isMoving = ((! memaccess_arbitration_isStuck) && (! memaccess_arbitration_removeIt)); // @ Pipeline.scala l146
  assign memaccess_arbitration_isFiring = ((memaccess_arbitration_isValid && (! memaccess_arbitration_isStuck)) && (! memaccess_arbitration_removeIt)); // @ Pipeline.scala l147
  assign writeback_arbitration_isStuckByOthers = (writeback_arbitration_haltByOther || 1'b0); // @ Pipeline.scala l144
  assign writeback_arbitration_isStuck = (writeback_arbitration_haltItself || writeback_arbitration_isStuckByOthers); // @ Pipeline.scala l145
  assign writeback_arbitration_isMoving = ((! writeback_arbitration_isStuck) && (! writeback_arbitration_removeIt)); // @ Pipeline.scala l146
  assign writeback_arbitration_isFiring = ((writeback_arbitration_isValid && (! writeback_arbitration_isStuck)) && (! writeback_arbitration_removeIt)); // @ Pipeline.scala l147
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      pc_next <= 32'h00000000; // @ Data.scala l409
      fetch_valid <= 1'b0; // @ Data.scala l409
      rsp_flush <= 1'b0; // @ Data.scala l409
      fetch_state <= IDLE; // @ Data.scala l409
      decode_DecodePlugin_branch_history <= 7'h00; // @ Data.scala l409
      decode_arbitration_isValid <= 1'b0; // @ Data.scala l409
      execute_arbitration_isValid <= 1'b0; // @ Data.scala l409
      memaccess_arbitration_isValid <= 1'b0; // @ Data.scala l409
      writeback_arbitration_isValid <= 1'b0; // @ Data.scala l409
    end else begin
      fetch_state <= fetch_state_next; // @ Reg.scala l39
      rsp_flush <= ((! ICachePlugin_icache_access_cmd_ready) ? (tmp_pc_next || fetch_FetchPlugin_bpu_predict_taken) : (! ICachePlugin_icache_access_rsp_valid)); // @ FetchPlugin.scala l65
      fetch_valid <= ((fetch_state_next == FETCH) ? 1'b1 : 1'b0); // @ FetchPlugin.scala l69
      pc_next <= (fetch_INT_PC ? fetch_CSR_PC : (tmp_pc_next ? execute_REDIRECT_PC_NEXT : (fetch_FetchPlugin_bpu_predict_taken ? fetch_BPU_PC_NEXT : tmp_pc_next_1))); // @ FetchPlugin.scala l70
      if(decode_arbitration_isFiring) begin
        decode_DecodePlugin_branch_history <= {decode_DecodePlugin_branch_history[5 : 0],(decode_DecodePlugin_is_jirl || decode_DecodePlugin_fetch_dec_branch)}; // @ DecodePlugin.scala l504
      end
      if(((! fetch_arbitration_isStuck) && (! fetch_arbitration_removeIt))) begin
        decode_arbitration_isValid <= fetch_arbitration_isValid; // @ Pipeline.scala l163
      end else begin
        if(((! decode_arbitration_isStuck) || decode_arbitration_removeIt)) begin
          decode_arbitration_isValid <= 1'b0; // @ Pipeline.scala l166
        end
      end
      if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt))) begin
        execute_arbitration_isValid <= decode_arbitration_isValid; // @ Pipeline.scala l163
      end else begin
        if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt)) begin
          execute_arbitration_isValid <= 1'b0; // @ Pipeline.scala l166
        end
      end
      if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt))) begin
        memaccess_arbitration_isValid <= execute_arbitration_isValid; // @ Pipeline.scala l163
      end else begin
        if(((! memaccess_arbitration_isStuck) || memaccess_arbitration_removeIt)) begin
          memaccess_arbitration_isValid <= 1'b0; // @ Pipeline.scala l166
        end
      end
      if(((! memaccess_arbitration_isStuck) && (! memaccess_arbitration_removeIt))) begin
        writeback_arbitration_isValid <= memaccess_arbitration_isValid; // @ Pipeline.scala l163
      end else begin
        if(((! writeback_arbitration_isStuck) || writeback_arbitration_removeIt)) begin
          writeback_arbitration_isValid <= 1'b0; // @ Pipeline.scala l166
        end
      end
    end
  end

  always @(posedge clk) begin
    if((! decode_arbitration_isStuck)) begin
      fetch_to_decode_PC <= fetch_PC; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_PC <= tmp_decode_to_execute_PC; // @ Pipeline.scala l126
    end
    if((! memaccess_arbitration_isStuck)) begin
      execute_to_memaccess_PC <= execute_PC; // @ Pipeline.scala l126
    end
    if((! writeback_arbitration_isStuck)) begin
      memaccess_to_writeback_PC <= memaccess_PC; // @ Pipeline.scala l126
    end
    if((! decode_arbitration_isStuck)) begin
      fetch_to_decode_PC_NEXT <= fetch_PC_NEXT; // @ Pipeline.scala l126
    end
    if((! decode_arbitration_isStuck)) begin
      fetch_to_decode_INSTRUCTION <= fetch_INSTRUCTION; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; // @ Pipeline.scala l126
    end
    if((! memaccess_arbitration_isStuck)) begin
      execute_to_memaccess_INSTRUCTION <= execute_INSTRUCTION; // @ Pipeline.scala l126
    end
    if((! writeback_arbitration_isStuck)) begin
      memaccess_to_writeback_INSTRUCTION <= memaccess_INSTRUCTION; // @ Pipeline.scala l126
    end
    if((! decode_arbitration_isStuck)) begin
      fetch_to_decode_PREDICT_TAKEN <= fetch_PREDICT_TAKEN; // @ Pipeline.scala l126
    end
    if((! decode_arbitration_isStuck)) begin
      fetch_to_decode_INT_PC <= fetch_INT_PC; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_INT_PC <= decode_INT_PC; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_ALU_CTRL <= decode_ALU_CTRL; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_RD_WEN <= decode_RD_WEN; // @ Pipeline.scala l126
    end
    if((! memaccess_arbitration_isStuck)) begin
      execute_to_memaccess_RD_WEN <= tmp_DecodePlugin_hazard_rs1_from_ex_1; // @ Pipeline.scala l126
    end
    if((! writeback_arbitration_isStuck)) begin
      memaccess_to_writeback_RD_WEN <= tmp_DecodePlugin_hazard_rs1_from_mem_1; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_RD_ADDR <= decode_RD_ADDR; // @ Pipeline.scala l126
    end
    if((! memaccess_arbitration_isStuck)) begin
      execute_to_memaccess_RD_ADDR <= tmp_DecodePlugin_hazard_rs1_from_ex; // @ Pipeline.scala l126
    end
    if((! writeback_arbitration_isStuck)) begin
      memaccess_to_writeback_RD_ADDR <= tmp_DecodePlugin_hazard_rs1_from_mem; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_RS1 <= decode_RS1; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_RS2 <= decode_RS2; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_LINK_ADDR <= decode_LINK_ADDR; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_REDIRECT_VALID <= tmp_fetch_arbitration_flushIt_2; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_REDIRECT_PC_NEXT <= tmp_decode_to_execute_REDIRECT_PC_NEXT; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_MEM_CTRL <= decode_MEM_CTRL; // @ Pipeline.scala l126
    end
    if((! memaccess_arbitration_isStuck)) begin
      execute_to_memaccess_MEM_CTRL <= execute_MEM_CTRL; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_IS_LOAD <= decode_IS_LOAD; // @ Pipeline.scala l126
    end
    if((! memaccess_arbitration_isStuck)) begin
      execute_to_memaccess_IS_LOAD <= execute_IS_LOAD; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_IS_STORE <= decode_IS_STORE; // @ Pipeline.scala l126
    end
    if((! memaccess_arbitration_isStuck)) begin
      execute_to_memaccess_IS_STORE <= execute_IS_STORE; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_MEM_WDATA <= decode_MEM_WDATA; // @ Pipeline.scala l126
    end
    if((! memaccess_arbitration_isStuck)) begin
      execute_to_memaccess_MEM_WDATA <= execute_MEM_WDATA; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_CSR_CTRL <= decode_CSR_CTRL; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_CSR_ADDR <= decode_CSR_ADDR; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_CSR_WEN <= decode_CSR_WEN; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_IS_CSR <= decode_IS_CSR; // @ Pipeline.scala l126
    end
    if((! memaccess_arbitration_isStuck)) begin
      execute_to_memaccess_IS_CSR <= execute_IS_CSR; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_CSR_CODE <= decode_CSR_CODE; // @ Pipeline.scala l126
    end
    if((! execute_arbitration_isStuck)) begin
      decode_to_execute_CSR_RDATA <= decode_CSR_RDATA; // @ Pipeline.scala l126
    end
    if((! memaccess_arbitration_isStuck)) begin
      execute_to_memaccess_CSR_RDATA <= execute_CSR_RDATA; // @ Pipeline.scala l126
    end
    if((! memaccess_arbitration_isStuck)) begin
      execute_to_memaccess_ALU_RESULT <= tmp_execute_to_memaccess_ALU_RESULT; // @ Pipeline.scala l126
    end
    if((! writeback_arbitration_isStuck)) begin
      memaccess_to_writeback_LLBIT_WE <= memaccess_LLBIT_WE; // @ Pipeline.scala l126
    end
    if((! writeback_arbitration_isStuck)) begin
      memaccess_to_writeback_LLBIT_DATA <= memaccess_LLBIT_DATA; // @ Pipeline.scala l126
    end
    if((! writeback_arbitration_isStuck)) begin
      memaccess_to_writeback_RD <= tmp_memaccess_to_writeback_RD; // @ Pipeline.scala l126
    end
  end


endmodule

module LLbitModule (
  output wire          read_ports_LLbit_data,
  input  wire          write_ports_LLbit_wen,
  input  wire          write_ports_LLbit_data,
  input  wire          clk,
  input  wire          reset
);

  reg                 LLbit;

  assign read_ports_LLbit_data = (write_ports_LLbit_wen ? write_ports_LLbit_data : LLbit); // @ LsuPlugin.scala l33
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      LLbit <= 1'b0; // @ Data.scala l409
    end else begin
      if(write_ports_LLbit_wen) begin
        LLbit <= write_ports_LLbit_data; // @ LsuPlugin.scala l30
      end
    end
  end


endmodule

module CsrRegfile (
  input  wire [13:0]   cpu_ports_waddr,
  input  wire          cpu_ports_wen,
  input  wire [31:0]   cpu_ports_wdata,
  input  wire [13:0]   cpu_ports_raddr,
  output reg  [31:0]   cpu_ports_rdata,
  output wire          cpu_ports_wvalid,
  input  wire          cpu_ports_is_ertn,
  input  wire          cpu_ports_is_syscall,
  input  wire          cpu_ports_is_adef,
  input  wire          cpu_ports_is_ine,
  input  wire          cpu_ports_is_break,
  input  wire          cpu_ports_is_ale,
  output reg           cpu_ports_int_pc,
  output reg  [31:0]   cpu_ports_pc_next,
  input  wire [14:0]   cpu_ports_excep_pc,
  input  wire [31:0]   cpu_ports_pc,
  input  wire          clk,
  input  wire          reset
);

  reg        [31:0]   crmd;
  reg        [31:0]   prmd;
  reg        [31:0]   estat;
  reg        [31:0]   era;
  reg        [31:0]   eentry;
  reg        [31:0]   save0;
  reg        [31:0]   save1;
  reg        [31:0]   save2;
  reg        [31:0]   save3;
  wire                is_excep;

  assign is_excep = ((((cpu_ports_is_syscall || cpu_ports_is_ertn) || cpu_ports_is_adef) || cpu_ports_is_ine) || cpu_ports_is_break); // @ BaseType.scala l305
  always @(*) begin
    cpu_ports_int_pc = 1'b0; // @ ExcepPlugin.scala l47
    if(is_excep) begin
      cpu_ports_int_pc = 1'b1; // @ ExcepPlugin.scala l57
    end
    if(cpu_ports_is_ertn) begin
      cpu_ports_int_pc = 1'b1; // @ ExcepPlugin.scala l84
    end
  end

  always @(*) begin
    cpu_ports_pc_next = 32'h00000000; // @ ExcepPlugin.scala l48
    if(is_excep) begin
      cpu_ports_pc_next = eentry; // @ ExcepPlugin.scala l58
    end
    if(cpu_ports_is_ertn) begin
      cpu_ports_pc_next = era; // @ ExcepPlugin.scala l85
    end
  end

  assign cpu_ports_wvalid = (crmd[1 : 0] == 2'b00); // @ ExcepPlugin.scala l50
  always @(*) begin
    if(((cpu_ports_wen && cpu_ports_wvalid) && (cpu_ports_raddr == cpu_ports_waddr))) begin
      cpu_ports_rdata = cpu_ports_wdata; // @ ExcepPlugin.scala l121
    end else begin
      case(cpu_ports_raddr)
        14'h0000 : begin
          cpu_ports_rdata = crmd; // @ ExcepPlugin.scala l125
        end
        14'h0001 : begin
          cpu_ports_rdata = prmd; // @ ExcepPlugin.scala l128
        end
        14'h0005 : begin
          cpu_ports_rdata = estat; // @ ExcepPlugin.scala l131
        end
        14'h0006 : begin
          cpu_ports_rdata = era; // @ ExcepPlugin.scala l134
        end
        14'h000c : begin
          cpu_ports_rdata = eentry; // @ ExcepPlugin.scala l137
        end
        14'h0030 : begin
          cpu_ports_rdata = save0; // @ ExcepPlugin.scala l140
        end
        14'h0031 : begin
          cpu_ports_rdata = save1; // @ ExcepPlugin.scala l143
        end
        14'h0032 : begin
          cpu_ports_rdata = save2; // @ ExcepPlugin.scala l146
        end
        14'h0033 : begin
          cpu_ports_rdata = save3; // @ ExcepPlugin.scala l152
        end
        default : begin
          cpu_ports_rdata = 32'h00000000; // @ ExcepPlugin.scala l149
        end
      endcase
    end
  end

  always @(posedge clk or posedge reset) begin
    if(reset) begin
      crmd <= {28'h0000000,4'b1000}; // @ Data.scala l409
      prmd <= 32'h00000000; // @ Data.scala l409
      estat <= 32'h00000000; // @ Data.scala l409
      era <= 32'h00000000; // @ Data.scala l409
      eentry <= 32'h00000000; // @ Data.scala l409
      save0 <= 32'h00000000; // @ Data.scala l409
      save1 <= 32'h00000000; // @ Data.scala l409
      save2 <= 32'h00000000; // @ Data.scala l409
      save3 <= 32'h00000000; // @ Data.scala l409
    end else begin
      if(is_excep) begin
        prmd[1 : 0] <= crmd[1 : 0]; // @ ExcepPlugin.scala l53
        prmd[2] <= crmd[2]; // @ ExcepPlugin.scala l54
        crmd[1 : 0] <= 2'b00; // @ ExcepPlugin.scala l55
        crmd[2] <= 1'b0; // @ ExcepPlugin.scala l56
        era <= cpu_ports_pc; // @ ExcepPlugin.scala l59
      end
      if(cpu_ports_is_adef) begin
        estat[21 : 16] <= 6'h08; // @ ExcepPlugin.scala l63
        estat[30 : 22] <= 9'h000; // @ ExcepPlugin.scala l64
      end else begin
        if(cpu_ports_is_ine) begin
          estat[21 : 16] <= 6'h0d; // @ ExcepPlugin.scala l66
        end else begin
          if(cpu_ports_is_syscall) begin
            estat[21 : 16] <= 6'h0b; // @ ExcepPlugin.scala l68
          end else begin
            if(cpu_ports_is_break) begin
              estat[21 : 16] <= 6'h0c; // @ ExcepPlugin.scala l70
            end else begin
              if(cpu_ports_is_ale) begin
                estat[21 : 16] <= 6'h08; // @ ExcepPlugin.scala l72
                estat[30 : 22] <= 9'h001; // @ ExcepPlugin.scala l73
              end
            end
          end
        end
      end
      if(cpu_ports_is_ertn) begin
        crmd[1 : 0] <= prmd[1 : 0]; // @ ExcepPlugin.scala l78
        crmd[2] <= prmd[2]; // @ ExcepPlugin.scala l79
        if((estat[21 : 16] == 6'h3f)) begin
          crmd[3] <= 1'b0; // @ ExcepPlugin.scala l81
          crmd[4] <= 1'b1; // @ ExcepPlugin.scala l82
        end
      end
      if((cpu_ports_wen && cpu_ports_wvalid)) begin
        case(cpu_ports_waddr)
          14'h0000 : begin
            crmd <= {23'h000000,cpu_ports_wdata[8 : 0]}; // @ ExcepPlugin.scala l91
          end
          14'h0001 : begin
            prmd <= {29'h00000000,cpu_ports_wdata[2 : 0]}; // @ ExcepPlugin.scala l94
          end
          14'h0005 : begin
            estat <= {30'h00000000,cpu_ports_wdata[1 : 0]}; // @ ExcepPlugin.scala l97
          end
          14'h0006 : begin
            era <= cpu_ports_wdata; // @ ExcepPlugin.scala l100
          end
          14'h000c : begin
            eentry <= {cpu_ports_wdata[31 : 6],6'h00}; // @ ExcepPlugin.scala l103
          end
          14'h0030 : begin
            save0 <= cpu_ports_wdata; // @ ExcepPlugin.scala l106
          end
          14'h0031 : begin
            save1 <= cpu_ports_wdata; // @ ExcepPlugin.scala l109
          end
          14'h0032 : begin
            save2 <= cpu_ports_wdata; // @ ExcepPlugin.scala l112
          end
          14'h0033 : begin
            save3 <= cpu_ports_wdata; // @ ExcepPlugin.scala l115
          end
          default : begin
          end
        endcase
      end
    end
  end


endmodule

module gshare_predictor (
  input  wire [31:0]   predict_pc,
  input  wire          predict_valid,
  output wire          predict_taken,
  output wire [6:0]    predict_history,
  output wire [31:0]   predict_pc_next,
  input  wire [31:0]   train_pc,
  input  wire          train_taken,
  input  wire          train_valid,
  input  wire [6:0]    train_history,
  input  wire          train_mispredicted,
  input  wire [31:0]   train_pc_next,
  input  wire          train_is_call,
  input  wire          train_is_return,
  input  wire          train_is_jump,
  input  wire          clk,
  input  wire          reset
);

  reg        [1:0]    tmp_GSHARE_pht_predict_taken;
  reg        [1:0]    tmp_11;
  wire                tmp_when;
  wire                tmp_when_1;
  wire                tmp_when_2;
  wire                tmp_when_3;
  wire       [1:0]    tmp_BTB_btb_alloc_index_valueNext;
  wire       [0:0]    tmp_BTB_btb_alloc_index_valueNext_1;
  wire                tmp_when_4;
  wire                tmp_when_5;
  wire                tmp_when_6;
  wire                tmp_when_7;
  wire                tmp_when_8;
  reg        [31:0]   tmp_RAS_ras_predict_pc;
  wire       [31:0]   tmp_predict_pc_next;
  reg        [6:0]    GSHARE_global_history_reg;
  reg        [1:0]    GSHARE_PHT_0;
  reg        [1:0]    GSHARE_PHT_1;
  reg        [1:0]    GSHARE_PHT_2;
  reg        [1:0]    GSHARE_PHT_3;
  reg        [1:0]    GSHARE_PHT_4;
  reg        [1:0]    GSHARE_PHT_5;
  reg        [1:0]    GSHARE_PHT_6;
  reg        [1:0]    GSHARE_PHT_7;
  reg        [1:0]    GSHARE_PHT_8;
  reg        [1:0]    GSHARE_PHT_9;
  reg        [1:0]    GSHARE_PHT_10;
  reg        [1:0]    GSHARE_PHT_11;
  reg        [1:0]    GSHARE_PHT_12;
  reg        [1:0]    GSHARE_PHT_13;
  reg        [1:0]    GSHARE_PHT_14;
  reg        [1:0]    GSHARE_PHT_15;
  reg        [1:0]    GSHARE_PHT_16;
  reg        [1:0]    GSHARE_PHT_17;
  reg        [1:0]    GSHARE_PHT_18;
  reg        [1:0]    GSHARE_PHT_19;
  reg        [1:0]    GSHARE_PHT_20;
  reg        [1:0]    GSHARE_PHT_21;
  reg        [1:0]    GSHARE_PHT_22;
  reg        [1:0]    GSHARE_PHT_23;
  reg        [1:0]    GSHARE_PHT_24;
  reg        [1:0]    GSHARE_PHT_25;
  reg        [1:0]    GSHARE_PHT_26;
  reg        [1:0]    GSHARE_PHT_27;
  reg        [1:0]    GSHARE_PHT_28;
  reg        [1:0]    GSHARE_PHT_29;
  reg        [1:0]    GSHARE_PHT_30;
  reg        [1:0]    GSHARE_PHT_31;
  reg        [1:0]    GSHARE_PHT_32;
  reg        [1:0]    GSHARE_PHT_33;
  reg        [1:0]    GSHARE_PHT_34;
  reg        [1:0]    GSHARE_PHT_35;
  reg        [1:0]    GSHARE_PHT_36;
  reg        [1:0]    GSHARE_PHT_37;
  reg        [1:0]    GSHARE_PHT_38;
  reg        [1:0]    GSHARE_PHT_39;
  reg        [1:0]    GSHARE_PHT_40;
  reg        [1:0]    GSHARE_PHT_41;
  reg        [1:0]    GSHARE_PHT_42;
  reg        [1:0]    GSHARE_PHT_43;
  reg        [1:0]    GSHARE_PHT_44;
  reg        [1:0]    GSHARE_PHT_45;
  reg        [1:0]    GSHARE_PHT_46;
  reg        [1:0]    GSHARE_PHT_47;
  reg        [1:0]    GSHARE_PHT_48;
  reg        [1:0]    GSHARE_PHT_49;
  reg        [1:0]    GSHARE_PHT_50;
  reg        [1:0]    GSHARE_PHT_51;
  reg        [1:0]    GSHARE_PHT_52;
  reg        [1:0]    GSHARE_PHT_53;
  reg        [1:0]    GSHARE_PHT_54;
  reg        [1:0]    GSHARE_PHT_55;
  reg        [1:0]    GSHARE_PHT_56;
  reg        [1:0]    GSHARE_PHT_57;
  reg        [1:0]    GSHARE_PHT_58;
  reg        [1:0]    GSHARE_PHT_59;
  reg        [1:0]    GSHARE_PHT_60;
  reg        [1:0]    GSHARE_PHT_61;
  reg        [1:0]    GSHARE_PHT_62;
  reg        [1:0]    GSHARE_PHT_63;
  reg        [1:0]    GSHARE_PHT_64;
  reg        [1:0]    GSHARE_PHT_65;
  reg        [1:0]    GSHARE_PHT_66;
  reg        [1:0]    GSHARE_PHT_67;
  reg        [1:0]    GSHARE_PHT_68;
  reg        [1:0]    GSHARE_PHT_69;
  reg        [1:0]    GSHARE_PHT_70;
  reg        [1:0]    GSHARE_PHT_71;
  reg        [1:0]    GSHARE_PHT_72;
  reg        [1:0]    GSHARE_PHT_73;
  reg        [1:0]    GSHARE_PHT_74;
  reg        [1:0]    GSHARE_PHT_75;
  reg        [1:0]    GSHARE_PHT_76;
  reg        [1:0]    GSHARE_PHT_77;
  reg        [1:0]    GSHARE_PHT_78;
  reg        [1:0]    GSHARE_PHT_79;
  reg        [1:0]    GSHARE_PHT_80;
  reg        [1:0]    GSHARE_PHT_81;
  reg        [1:0]    GSHARE_PHT_82;
  reg        [1:0]    GSHARE_PHT_83;
  reg        [1:0]    GSHARE_PHT_84;
  reg        [1:0]    GSHARE_PHT_85;
  reg        [1:0]    GSHARE_PHT_86;
  reg        [1:0]    GSHARE_PHT_87;
  reg        [1:0]    GSHARE_PHT_88;
  reg        [1:0]    GSHARE_PHT_89;
  reg        [1:0]    GSHARE_PHT_90;
  reg        [1:0]    GSHARE_PHT_91;
  reg        [1:0]    GSHARE_PHT_92;
  reg        [1:0]    GSHARE_PHT_93;
  reg        [1:0]    GSHARE_PHT_94;
  reg        [1:0]    GSHARE_PHT_95;
  reg        [1:0]    GSHARE_PHT_96;
  reg        [1:0]    GSHARE_PHT_97;
  reg        [1:0]    GSHARE_PHT_98;
  reg        [1:0]    GSHARE_PHT_99;
  reg        [1:0]    GSHARE_PHT_100;
  reg        [1:0]    GSHARE_PHT_101;
  reg        [1:0]    GSHARE_PHT_102;
  reg        [1:0]    GSHARE_PHT_103;
  reg        [1:0]    GSHARE_PHT_104;
  reg        [1:0]    GSHARE_PHT_105;
  reg        [1:0]    GSHARE_PHT_106;
  reg        [1:0]    GSHARE_PHT_107;
  reg        [1:0]    GSHARE_PHT_108;
  reg        [1:0]    GSHARE_PHT_109;
  reg        [1:0]    GSHARE_PHT_110;
  reg        [1:0]    GSHARE_PHT_111;
  reg        [1:0]    GSHARE_PHT_112;
  reg        [1:0]    GSHARE_PHT_113;
  reg        [1:0]    GSHARE_PHT_114;
  reg        [1:0]    GSHARE_PHT_115;
  reg        [1:0]    GSHARE_PHT_116;
  reg        [1:0]    GSHARE_PHT_117;
  reg        [1:0]    GSHARE_PHT_118;
  reg        [1:0]    GSHARE_PHT_119;
  reg        [1:0]    GSHARE_PHT_120;
  reg        [1:0]    GSHARE_PHT_121;
  reg        [1:0]    GSHARE_PHT_122;
  reg        [1:0]    GSHARE_PHT_123;
  reg        [1:0]    GSHARE_PHT_124;
  reg        [1:0]    GSHARE_PHT_125;
  reg        [1:0]    GSHARE_PHT_126;
  reg        [1:0]    GSHARE_PHT_127;
  wire       [6:0]    GSHARE_predict_index;
  wire       [6:0]    GSHARE_train_index;
  wire                GSHARE_pht_predict_taken;
  wire       [127:0]  tmp_1;
  reg        [1:0]    tmp_GSHARE_PHT_0;
  reg        [3:0]    BTB_valid;
  reg        [31:0]   BTB_source_pc_0;
  reg        [31:0]   BTB_source_pc_1;
  reg        [31:0]   BTB_source_pc_2;
  reg        [31:0]   BTB_source_pc_3;
  reg        [3:0]    BTB_call;
  reg        [3:0]    BTB_ret;
  reg        [3:0]    BTB_jump;
  reg        [31:0]   BTB_target_pc_0;
  reg        [31:0]   BTB_target_pc_1;
  reg        [31:0]   BTB_target_pc_2;
  reg        [31:0]   BTB_target_pc_3;
  reg                 BTB_is_matched;
  reg                 BTB_is_call;
  reg                 BTB_is_return;
  reg                 BTB_is_jump;
  reg        [31:0]   BTB_target_pc_read;
  wire       [1:0]    BTB_btb_write_index;
  reg                 BTB_btb_alloc_index_willIncrement;
  reg                 BTB_btb_alloc_index_willClear;
  reg        [1:0]    BTB_btb_alloc_index_valueNext;
  reg        [1:0]    BTB_btb_alloc_index_value;
  wire                BTB_btb_alloc_index_willOverflowIfInc;
  wire                BTB_btb_alloc_index_willOverflow;
  reg                 BTB_btb_is_hit_vec_0;
  reg                 BTB_btb_is_hit_vec_1;
  reg                 BTB_btb_is_hit_vec_2;
  reg                 BTB_btb_is_hit_vec_3;
  reg                 BTB_btb_is_miss_vec_0;
  reg                 BTB_btb_is_miss_vec_1;
  reg                 BTB_btb_is_miss_vec_2;
  reg                 BTB_btb_is_miss_vec_3;
  wire                BTB_btb_is_hit;
  wire                BTB_btb_is_miss;
  wire                tmp_BTB_btb_write_index;
  wire                tmp_BTB_btb_write_index_1;
  wire       [3:0]    tmp_2;
  wire       [3:0]    tmp_3;
  wire       [3:0]    tmp_4;
  wire       [3:0]    tmp_5;
  reg        [31:0]   RAS_ras_regfile_0;
  reg        [31:0]   RAS_ras_regfile_1;
  reg        [31:0]   RAS_ras_regfile_2;
  reg        [31:0]   RAS_ras_regfile_3;
  reg        [1:0]    RAS_ras_next_index;
  reg        [1:0]    RAS_ras_curr_index;
  reg        [1:0]    RAS_ras_next_index_proven;
  reg        [1:0]    RAS_ras_curr_index_proven;
  wire       [31:0]   RAS_ras_predict_pc;
  wire                RAS_ras_call_matched;
  wire                RAS_ras_ret_matched;
  wire       [3:0]    tmp_6;
  wire                tmp_7;
  wire                tmp_8;
  wire                tmp_9;
  wire                tmp_10;
  wire       [31:0]   tmp_RAS_ras_regfile_0;
  wire       [31:0]   tmp_RAS_ras_regfile_0_1;

  assign tmp_when = ((BTB_source_pc_0 == predict_pc) && BTB_valid[0]);
  assign tmp_when_1 = ((BTB_source_pc_1 == predict_pc) && BTB_valid[1]);
  assign tmp_when_2 = ((BTB_source_pc_2 == predict_pc) && BTB_valid[2]);
  assign tmp_when_3 = ((BTB_source_pc_3 == predict_pc) && BTB_valid[3]);
  assign tmp_when_4 = (train_valid && train_taken);
  assign tmp_when_5 = (train_valid && train_taken);
  assign tmp_when_6 = (train_valid && train_taken);
  assign tmp_when_7 = (train_valid && train_taken);
  assign tmp_when_8 = ((train_mispredicted && train_valid) && train_is_call);
  assign tmp_BTB_btb_alloc_index_valueNext_1 = BTB_btb_alloc_index_willIncrement;
  assign tmp_BTB_btb_alloc_index_valueNext = {1'd0, tmp_BTB_btb_alloc_index_valueNext_1};
  assign tmp_predict_pc_next = (predict_pc + 32'h00000004);
  always @(*) begin
    case(GSHARE_predict_index)
      7'b0000000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_0;
      7'b0000001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_1;
      7'b0000010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_2;
      7'b0000011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_3;
      7'b0000100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_4;
      7'b0000101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_5;
      7'b0000110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_6;
      7'b0000111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_7;
      7'b0001000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_8;
      7'b0001001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_9;
      7'b0001010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_10;
      7'b0001011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_11;
      7'b0001100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_12;
      7'b0001101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_13;
      7'b0001110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_14;
      7'b0001111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_15;
      7'b0010000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_16;
      7'b0010001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_17;
      7'b0010010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_18;
      7'b0010011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_19;
      7'b0010100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_20;
      7'b0010101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_21;
      7'b0010110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_22;
      7'b0010111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_23;
      7'b0011000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_24;
      7'b0011001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_25;
      7'b0011010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_26;
      7'b0011011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_27;
      7'b0011100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_28;
      7'b0011101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_29;
      7'b0011110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_30;
      7'b0011111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_31;
      7'b0100000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_32;
      7'b0100001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_33;
      7'b0100010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_34;
      7'b0100011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_35;
      7'b0100100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_36;
      7'b0100101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_37;
      7'b0100110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_38;
      7'b0100111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_39;
      7'b0101000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_40;
      7'b0101001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_41;
      7'b0101010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_42;
      7'b0101011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_43;
      7'b0101100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_44;
      7'b0101101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_45;
      7'b0101110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_46;
      7'b0101111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_47;
      7'b0110000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_48;
      7'b0110001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_49;
      7'b0110010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_50;
      7'b0110011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_51;
      7'b0110100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_52;
      7'b0110101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_53;
      7'b0110110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_54;
      7'b0110111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_55;
      7'b0111000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_56;
      7'b0111001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_57;
      7'b0111010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_58;
      7'b0111011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_59;
      7'b0111100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_60;
      7'b0111101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_61;
      7'b0111110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_62;
      7'b0111111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_63;
      7'b1000000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_64;
      7'b1000001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_65;
      7'b1000010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_66;
      7'b1000011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_67;
      7'b1000100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_68;
      7'b1000101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_69;
      7'b1000110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_70;
      7'b1000111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_71;
      7'b1001000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_72;
      7'b1001001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_73;
      7'b1001010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_74;
      7'b1001011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_75;
      7'b1001100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_76;
      7'b1001101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_77;
      7'b1001110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_78;
      7'b1001111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_79;
      7'b1010000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_80;
      7'b1010001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_81;
      7'b1010010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_82;
      7'b1010011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_83;
      7'b1010100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_84;
      7'b1010101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_85;
      7'b1010110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_86;
      7'b1010111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_87;
      7'b1011000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_88;
      7'b1011001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_89;
      7'b1011010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_90;
      7'b1011011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_91;
      7'b1011100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_92;
      7'b1011101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_93;
      7'b1011110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_94;
      7'b1011111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_95;
      7'b1100000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_96;
      7'b1100001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_97;
      7'b1100010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_98;
      7'b1100011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_99;
      7'b1100100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_100;
      7'b1100101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_101;
      7'b1100110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_102;
      7'b1100111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_103;
      7'b1101000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_104;
      7'b1101001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_105;
      7'b1101010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_106;
      7'b1101011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_107;
      7'b1101100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_108;
      7'b1101101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_109;
      7'b1101110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_110;
      7'b1101111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_111;
      7'b1110000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_112;
      7'b1110001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_113;
      7'b1110010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_114;
      7'b1110011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_115;
      7'b1110100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_116;
      7'b1110101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_117;
      7'b1110110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_118;
      7'b1110111 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_119;
      7'b1111000 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_120;
      7'b1111001 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_121;
      7'b1111010 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_122;
      7'b1111011 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_123;
      7'b1111100 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_124;
      7'b1111101 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_125;
      7'b1111110 : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_126;
      default : tmp_GSHARE_pht_predict_taken = GSHARE_PHT_127;
    endcase
  end

  always @(*) begin
    case(GSHARE_train_index)
      7'b0000000 : tmp_11 = GSHARE_PHT_0;
      7'b0000001 : tmp_11 = GSHARE_PHT_1;
      7'b0000010 : tmp_11 = GSHARE_PHT_2;
      7'b0000011 : tmp_11 = GSHARE_PHT_3;
      7'b0000100 : tmp_11 = GSHARE_PHT_4;
      7'b0000101 : tmp_11 = GSHARE_PHT_5;
      7'b0000110 : tmp_11 = GSHARE_PHT_6;
      7'b0000111 : tmp_11 = GSHARE_PHT_7;
      7'b0001000 : tmp_11 = GSHARE_PHT_8;
      7'b0001001 : tmp_11 = GSHARE_PHT_9;
      7'b0001010 : tmp_11 = GSHARE_PHT_10;
      7'b0001011 : tmp_11 = GSHARE_PHT_11;
      7'b0001100 : tmp_11 = GSHARE_PHT_12;
      7'b0001101 : tmp_11 = GSHARE_PHT_13;
      7'b0001110 : tmp_11 = GSHARE_PHT_14;
      7'b0001111 : tmp_11 = GSHARE_PHT_15;
      7'b0010000 : tmp_11 = GSHARE_PHT_16;
      7'b0010001 : tmp_11 = GSHARE_PHT_17;
      7'b0010010 : tmp_11 = GSHARE_PHT_18;
      7'b0010011 : tmp_11 = GSHARE_PHT_19;
      7'b0010100 : tmp_11 = GSHARE_PHT_20;
      7'b0010101 : tmp_11 = GSHARE_PHT_21;
      7'b0010110 : tmp_11 = GSHARE_PHT_22;
      7'b0010111 : tmp_11 = GSHARE_PHT_23;
      7'b0011000 : tmp_11 = GSHARE_PHT_24;
      7'b0011001 : tmp_11 = GSHARE_PHT_25;
      7'b0011010 : tmp_11 = GSHARE_PHT_26;
      7'b0011011 : tmp_11 = GSHARE_PHT_27;
      7'b0011100 : tmp_11 = GSHARE_PHT_28;
      7'b0011101 : tmp_11 = GSHARE_PHT_29;
      7'b0011110 : tmp_11 = GSHARE_PHT_30;
      7'b0011111 : tmp_11 = GSHARE_PHT_31;
      7'b0100000 : tmp_11 = GSHARE_PHT_32;
      7'b0100001 : tmp_11 = GSHARE_PHT_33;
      7'b0100010 : tmp_11 = GSHARE_PHT_34;
      7'b0100011 : tmp_11 = GSHARE_PHT_35;
      7'b0100100 : tmp_11 = GSHARE_PHT_36;
      7'b0100101 : tmp_11 = GSHARE_PHT_37;
      7'b0100110 : tmp_11 = GSHARE_PHT_38;
      7'b0100111 : tmp_11 = GSHARE_PHT_39;
      7'b0101000 : tmp_11 = GSHARE_PHT_40;
      7'b0101001 : tmp_11 = GSHARE_PHT_41;
      7'b0101010 : tmp_11 = GSHARE_PHT_42;
      7'b0101011 : tmp_11 = GSHARE_PHT_43;
      7'b0101100 : tmp_11 = GSHARE_PHT_44;
      7'b0101101 : tmp_11 = GSHARE_PHT_45;
      7'b0101110 : tmp_11 = GSHARE_PHT_46;
      7'b0101111 : tmp_11 = GSHARE_PHT_47;
      7'b0110000 : tmp_11 = GSHARE_PHT_48;
      7'b0110001 : tmp_11 = GSHARE_PHT_49;
      7'b0110010 : tmp_11 = GSHARE_PHT_50;
      7'b0110011 : tmp_11 = GSHARE_PHT_51;
      7'b0110100 : tmp_11 = GSHARE_PHT_52;
      7'b0110101 : tmp_11 = GSHARE_PHT_53;
      7'b0110110 : tmp_11 = GSHARE_PHT_54;
      7'b0110111 : tmp_11 = GSHARE_PHT_55;
      7'b0111000 : tmp_11 = GSHARE_PHT_56;
      7'b0111001 : tmp_11 = GSHARE_PHT_57;
      7'b0111010 : tmp_11 = GSHARE_PHT_58;
      7'b0111011 : tmp_11 = GSHARE_PHT_59;
      7'b0111100 : tmp_11 = GSHARE_PHT_60;
      7'b0111101 : tmp_11 = GSHARE_PHT_61;
      7'b0111110 : tmp_11 = GSHARE_PHT_62;
      7'b0111111 : tmp_11 = GSHARE_PHT_63;
      7'b1000000 : tmp_11 = GSHARE_PHT_64;
      7'b1000001 : tmp_11 = GSHARE_PHT_65;
      7'b1000010 : tmp_11 = GSHARE_PHT_66;
      7'b1000011 : tmp_11 = GSHARE_PHT_67;
      7'b1000100 : tmp_11 = GSHARE_PHT_68;
      7'b1000101 : tmp_11 = GSHARE_PHT_69;
      7'b1000110 : tmp_11 = GSHARE_PHT_70;
      7'b1000111 : tmp_11 = GSHARE_PHT_71;
      7'b1001000 : tmp_11 = GSHARE_PHT_72;
      7'b1001001 : tmp_11 = GSHARE_PHT_73;
      7'b1001010 : tmp_11 = GSHARE_PHT_74;
      7'b1001011 : tmp_11 = GSHARE_PHT_75;
      7'b1001100 : tmp_11 = GSHARE_PHT_76;
      7'b1001101 : tmp_11 = GSHARE_PHT_77;
      7'b1001110 : tmp_11 = GSHARE_PHT_78;
      7'b1001111 : tmp_11 = GSHARE_PHT_79;
      7'b1010000 : tmp_11 = GSHARE_PHT_80;
      7'b1010001 : tmp_11 = GSHARE_PHT_81;
      7'b1010010 : tmp_11 = GSHARE_PHT_82;
      7'b1010011 : tmp_11 = GSHARE_PHT_83;
      7'b1010100 : tmp_11 = GSHARE_PHT_84;
      7'b1010101 : tmp_11 = GSHARE_PHT_85;
      7'b1010110 : tmp_11 = GSHARE_PHT_86;
      7'b1010111 : tmp_11 = GSHARE_PHT_87;
      7'b1011000 : tmp_11 = GSHARE_PHT_88;
      7'b1011001 : tmp_11 = GSHARE_PHT_89;
      7'b1011010 : tmp_11 = GSHARE_PHT_90;
      7'b1011011 : tmp_11 = GSHARE_PHT_91;
      7'b1011100 : tmp_11 = GSHARE_PHT_92;
      7'b1011101 : tmp_11 = GSHARE_PHT_93;
      7'b1011110 : tmp_11 = GSHARE_PHT_94;
      7'b1011111 : tmp_11 = GSHARE_PHT_95;
      7'b1100000 : tmp_11 = GSHARE_PHT_96;
      7'b1100001 : tmp_11 = GSHARE_PHT_97;
      7'b1100010 : tmp_11 = GSHARE_PHT_98;
      7'b1100011 : tmp_11 = GSHARE_PHT_99;
      7'b1100100 : tmp_11 = GSHARE_PHT_100;
      7'b1100101 : tmp_11 = GSHARE_PHT_101;
      7'b1100110 : tmp_11 = GSHARE_PHT_102;
      7'b1100111 : tmp_11 = GSHARE_PHT_103;
      7'b1101000 : tmp_11 = GSHARE_PHT_104;
      7'b1101001 : tmp_11 = GSHARE_PHT_105;
      7'b1101010 : tmp_11 = GSHARE_PHT_106;
      7'b1101011 : tmp_11 = GSHARE_PHT_107;
      7'b1101100 : tmp_11 = GSHARE_PHT_108;
      7'b1101101 : tmp_11 = GSHARE_PHT_109;
      7'b1101110 : tmp_11 = GSHARE_PHT_110;
      7'b1101111 : tmp_11 = GSHARE_PHT_111;
      7'b1110000 : tmp_11 = GSHARE_PHT_112;
      7'b1110001 : tmp_11 = GSHARE_PHT_113;
      7'b1110010 : tmp_11 = GSHARE_PHT_114;
      7'b1110011 : tmp_11 = GSHARE_PHT_115;
      7'b1110100 : tmp_11 = GSHARE_PHT_116;
      7'b1110101 : tmp_11 = GSHARE_PHT_117;
      7'b1110110 : tmp_11 = GSHARE_PHT_118;
      7'b1110111 : tmp_11 = GSHARE_PHT_119;
      7'b1111000 : tmp_11 = GSHARE_PHT_120;
      7'b1111001 : tmp_11 = GSHARE_PHT_121;
      7'b1111010 : tmp_11 = GSHARE_PHT_122;
      7'b1111011 : tmp_11 = GSHARE_PHT_123;
      7'b1111100 : tmp_11 = GSHARE_PHT_124;
      7'b1111101 : tmp_11 = GSHARE_PHT_125;
      7'b1111110 : tmp_11 = GSHARE_PHT_126;
      default : tmp_11 = GSHARE_PHT_127;
    endcase
  end

  always @(*) begin
    case(RAS_ras_curr_index)
      2'b00 : tmp_RAS_ras_predict_pc = RAS_ras_regfile_0;
      2'b01 : tmp_RAS_ras_predict_pc = RAS_ras_regfile_1;
      2'b10 : tmp_RAS_ras_predict_pc = RAS_ras_regfile_2;
      default : tmp_RAS_ras_predict_pc = RAS_ras_regfile_3;
    endcase
  end

  assign GSHARE_predict_index = (predict_pc[8 : 2] ^ GSHARE_global_history_reg); // @ BaseType.scala l299
  assign GSHARE_train_index = (train_pc[8 : 2] ^ train_history); // @ BaseType.scala l299
  assign GSHARE_pht_predict_taken = tmp_GSHARE_pht_predict_taken[1]; // @ BaseType.scala l305
  assign tmp_1 = ({127'd0,1'b1} <<< GSHARE_train_index); // @ BaseType.scala l299
  always @(*) begin
    case(tmp_11)
      2'b00 : begin
        tmp_GSHARE_PHT_0 = (train_taken ? 2'b01 : 2'b00); // @ Misc.scala l254
      end
      2'b01 : begin
        tmp_GSHARE_PHT_0 = (train_taken ? 2'b10 : 2'b00); // @ Misc.scala l254
      end
      2'b10 : begin
        tmp_GSHARE_PHT_0 = (train_taken ? 2'b11 : 2'b01); // @ Misc.scala l254
      end
      default : begin
        tmp_GSHARE_PHT_0 = (train_taken ? 2'b10 : 2'b11); // @ Misc.scala l254
      end
    endcase
  end

  always @(*) begin
    BTB_is_matched = 1'b0; // @ Predictor.scala l66
    if(tmp_when) begin
      BTB_is_matched = 1'b1; // @ Predictor.scala l75
    end
    if(tmp_when_1) begin
      BTB_is_matched = 1'b1; // @ Predictor.scala l75
    end
    if(tmp_when_2) begin
      BTB_is_matched = 1'b1; // @ Predictor.scala l75
    end
    if(tmp_when_3) begin
      BTB_is_matched = 1'b1; // @ Predictor.scala l75
    end
  end

  always @(*) begin
    BTB_is_call = 1'b0; // @ Predictor.scala l67
    if(tmp_when) begin
      BTB_is_call = BTB_call[0]; // @ Predictor.scala l76
    end
    if(tmp_when_1) begin
      BTB_is_call = BTB_call[1]; // @ Predictor.scala l76
    end
    if(tmp_when_2) begin
      BTB_is_call = BTB_call[2]; // @ Predictor.scala l76
    end
    if(tmp_when_3) begin
      BTB_is_call = BTB_call[3]; // @ Predictor.scala l76
    end
  end

  always @(*) begin
    BTB_is_return = 1'b0; // @ Predictor.scala l68
    if(tmp_when) begin
      BTB_is_return = BTB_ret[0]; // @ Predictor.scala l77
    end
    if(tmp_when_1) begin
      BTB_is_return = BTB_ret[1]; // @ Predictor.scala l77
    end
    if(tmp_when_2) begin
      BTB_is_return = BTB_ret[2]; // @ Predictor.scala l77
    end
    if(tmp_when_3) begin
      BTB_is_return = BTB_ret[3]; // @ Predictor.scala l77
    end
  end

  always @(*) begin
    BTB_is_jump = 1'b0; // @ Predictor.scala l69
    if(tmp_when) begin
      BTB_is_jump = BTB_jump[0]; // @ Predictor.scala l78
    end
    if(tmp_when_1) begin
      BTB_is_jump = BTB_jump[1]; // @ Predictor.scala l78
    end
    if(tmp_when_2) begin
      BTB_is_jump = BTB_jump[2]; // @ Predictor.scala l78
    end
    if(tmp_when_3) begin
      BTB_is_jump = BTB_jump[3]; // @ Predictor.scala l78
    end
  end

  always @(*) begin
    BTB_target_pc_read = 32'h00000000; // @ Expression.scala l2360
    if(tmp_when) begin
      BTB_target_pc_read = BTB_target_pc_0; // @ Predictor.scala l79
    end
    if(tmp_when_1) begin
      BTB_target_pc_read = BTB_target_pc_1; // @ Predictor.scala l79
    end
    if(tmp_when_2) begin
      BTB_target_pc_read = BTB_target_pc_2; // @ Predictor.scala l79
    end
    if(tmp_when_3) begin
      BTB_target_pc_read = BTB_target_pc_3; // @ Predictor.scala l79
    end
  end

  always @(*) begin
    BTB_btb_alloc_index_willIncrement = 1'b0; // @ Utils.scala l582
    if(BTB_btb_is_miss) begin
      if(!BTB_btb_alloc_index_willOverflowIfInc) begin
        BTB_btb_alloc_index_willIncrement = 1'b1; // @ Utils.scala l586
      end
    end
  end

  always @(*) begin
    BTB_btb_alloc_index_willClear = 1'b0; // @ Utils.scala l583
    if(BTB_btb_is_miss) begin
      if(BTB_btb_alloc_index_willOverflowIfInc) begin
        BTB_btb_alloc_index_willClear = 1'b1; // @ Utils.scala l585
      end
    end
  end

  assign BTB_btb_alloc_index_willOverflowIfInc = (BTB_btb_alloc_index_value == 2'b11); // @ BaseType.scala l305
  assign BTB_btb_alloc_index_willOverflow = (BTB_btb_alloc_index_willOverflowIfInc && BTB_btb_alloc_index_willIncrement); // @ BaseType.scala l305
  always @(*) begin
    BTB_btb_alloc_index_valueNext = (BTB_btb_alloc_index_value + tmp_BTB_btb_alloc_index_valueNext); // @ Utils.scala l594
    if(BTB_btb_alloc_index_willClear) begin
      BTB_btb_alloc_index_valueNext = 2'b00; // @ Utils.scala l604
    end
  end

  assign BTB_btb_is_hit = (|{BTB_btb_is_hit_vec_3,{BTB_btb_is_hit_vec_2,{BTB_btb_is_hit_vec_1,BTB_btb_is_hit_vec_0}}}); // @ BaseType.scala l312
  assign BTB_btb_is_miss = (|{BTB_btb_is_miss_vec_3,{BTB_btb_is_miss_vec_2,{BTB_btb_is_miss_vec_1,BTB_btb_is_miss_vec_0}}}); // @ BaseType.scala l312
  always @(*) begin
    if(tmp_when_4) begin
      BTB_btb_is_hit_vec_0 = (((BTB_source_pc_0 == train_pc) && BTB_valid[0]) ? 1'b1 : 1'b0); // @ Predictor.scala l93
    end else begin
      BTB_btb_is_hit_vec_0 = 1'b0; // @ Predictor.scala l96
    end
  end

  always @(*) begin
    if(tmp_when_4) begin
      BTB_btb_is_miss_vec_0 = (((BTB_source_pc_0 != train_pc) || (! BTB_valid[0])) ? 1'b1 : 1'b0); // @ Predictor.scala l94
    end else begin
      BTB_btb_is_miss_vec_0 = 1'b0; // @ Predictor.scala l97
    end
  end

  always @(*) begin
    if(tmp_when_5) begin
      BTB_btb_is_hit_vec_1 = (((BTB_source_pc_1 == train_pc) && BTB_valid[1]) ? 1'b1 : 1'b0); // @ Predictor.scala l93
    end else begin
      BTB_btb_is_hit_vec_1 = 1'b0; // @ Predictor.scala l96
    end
  end

  always @(*) begin
    if(tmp_when_5) begin
      BTB_btb_is_miss_vec_1 = (((BTB_source_pc_1 != train_pc) || (! BTB_valid[1])) ? 1'b1 : 1'b0); // @ Predictor.scala l94
    end else begin
      BTB_btb_is_miss_vec_1 = 1'b0; // @ Predictor.scala l97
    end
  end

  always @(*) begin
    if(tmp_when_6) begin
      BTB_btb_is_hit_vec_2 = (((BTB_source_pc_2 == train_pc) && BTB_valid[2]) ? 1'b1 : 1'b0); // @ Predictor.scala l93
    end else begin
      BTB_btb_is_hit_vec_2 = 1'b0; // @ Predictor.scala l96
    end
  end

  always @(*) begin
    if(tmp_when_6) begin
      BTB_btb_is_miss_vec_2 = (((BTB_source_pc_2 != train_pc) || (! BTB_valid[2])) ? 1'b1 : 1'b0); // @ Predictor.scala l94
    end else begin
      BTB_btb_is_miss_vec_2 = 1'b0; // @ Predictor.scala l97
    end
  end

  always @(*) begin
    if(tmp_when_7) begin
      BTB_btb_is_hit_vec_3 = (((BTB_source_pc_3 == train_pc) && BTB_valid[3]) ? 1'b1 : 1'b0); // @ Predictor.scala l93
    end else begin
      BTB_btb_is_hit_vec_3 = 1'b0; // @ Predictor.scala l96
    end
  end

  always @(*) begin
    if(tmp_when_7) begin
      BTB_btb_is_miss_vec_3 = (((BTB_source_pc_3 != train_pc) || (! BTB_valid[3])) ? 1'b1 : 1'b0); // @ Predictor.scala l94
    end else begin
      BTB_btb_is_miss_vec_3 = 1'b0; // @ Predictor.scala l97
    end
  end

  assign tmp_BTB_btb_write_index = (BTB_btb_is_hit_vec_1 || BTB_btb_is_hit_vec_3); // @ BaseType.scala l305
  assign tmp_BTB_btb_write_index_1 = (BTB_btb_is_hit_vec_2 || BTB_btb_is_hit_vec_3); // @ BaseType.scala l305
  assign BTB_btb_write_index = {tmp_BTB_btb_write_index_1,tmp_BTB_btb_write_index}; // @ Predictor.scala l101
  assign tmp_2 = ({3'd0,1'b1} <<< BTB_btb_write_index); // @ BaseType.scala l299
  assign tmp_3 = ({3'd0,1'b1} <<< BTB_btb_write_index); // @ BaseType.scala l299
  assign tmp_4 = ({3'd0,1'b1} <<< BTB_btb_alloc_index_value); // @ BaseType.scala l299
  assign tmp_5 = ({3'd0,1'b1} <<< BTB_btb_alloc_index_value); // @ BaseType.scala l299
  assign RAS_ras_call_matched = (BTB_is_matched && BTB_is_call); // @ BaseType.scala l305
  assign RAS_ras_ret_matched = (BTB_is_matched && BTB_is_return); // @ BaseType.scala l305
  always @(*) begin
    if((train_valid && train_is_call)) begin
      RAS_ras_next_index_proven = (RAS_ras_curr_index_proven + 2'b01); // @ Predictor.scala l139
    end else begin
      if((train_valid && train_is_return)) begin
        RAS_ras_next_index_proven = (RAS_ras_curr_index_proven - 2'b01); // @ Predictor.scala l141
      end else begin
        RAS_ras_next_index_proven = RAS_ras_curr_index_proven; // @ Predictor.scala l143
      end
    end
  end

  always @(*) begin
    if(((train_mispredicted && train_valid) && train_is_call)) begin
      RAS_ras_next_index = (RAS_ras_curr_index_proven + 2'b01); // @ Predictor.scala l148
    end else begin
      if(((train_mispredicted && train_valid) && train_is_return)) begin
        RAS_ras_next_index = (RAS_ras_curr_index_proven - 2'b01); // @ Predictor.scala l150
      end else begin
        if(RAS_ras_call_matched) begin
          RAS_ras_next_index = (RAS_ras_curr_index + 2'b01); // @ Predictor.scala l152
        end else begin
          if(RAS_ras_ret_matched) begin
            RAS_ras_next_index = (RAS_ras_curr_index - 2'b01); // @ Predictor.scala l154
          end else begin
            RAS_ras_next_index = RAS_ras_curr_index; // @ Predictor.scala l156
          end
        end
      end
    end
  end

  assign tmp_6 = ({3'd0,1'b1} <<< RAS_ras_next_index); // @ BaseType.scala l299
  assign tmp_7 = tmp_6[0]; // @ BaseType.scala l305
  assign tmp_8 = tmp_6[1]; // @ BaseType.scala l305
  assign tmp_9 = tmp_6[2]; // @ BaseType.scala l305
  assign tmp_10 = tmp_6[3]; // @ BaseType.scala l305
  assign tmp_RAS_ras_regfile_0 = (train_pc + 32'h00000004); // @ BaseType.scala l299
  assign tmp_RAS_ras_regfile_0_1 = (predict_pc + 32'h00000004); // @ BaseType.scala l299
  assign RAS_ras_predict_pc = tmp_RAS_ras_predict_pc; // @ Predictor.scala l173
  assign predict_history = GSHARE_global_history_reg; // @ Predictor.scala l177
  assign predict_taken = (BTB_is_matched && (((GSHARE_pht_predict_taken || BTB_is_jump) || BTB_is_call) || BTB_is_return)); // @ Predictor.scala l178
  assign predict_pc_next = (RAS_ras_ret_matched ? RAS_ras_predict_pc : ((BTB_is_matched && ((GSHARE_pht_predict_taken || BTB_is_jump) || BTB_is_call)) ? BTB_target_pc_read : tmp_predict_pc_next)); // @ Predictor.scala l179
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      GSHARE_global_history_reg <= 7'h00; // @ Data.scala l409
      GSHARE_PHT_0 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_1 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_2 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_3 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_4 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_5 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_6 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_7 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_8 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_9 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_10 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_11 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_12 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_13 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_14 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_15 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_16 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_17 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_18 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_19 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_20 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_21 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_22 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_23 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_24 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_25 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_26 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_27 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_28 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_29 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_30 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_31 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_32 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_33 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_34 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_35 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_36 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_37 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_38 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_39 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_40 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_41 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_42 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_43 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_44 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_45 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_46 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_47 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_48 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_49 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_50 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_51 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_52 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_53 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_54 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_55 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_56 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_57 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_58 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_59 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_60 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_61 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_62 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_63 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_64 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_65 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_66 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_67 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_68 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_69 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_70 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_71 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_72 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_73 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_74 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_75 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_76 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_77 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_78 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_79 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_80 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_81 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_82 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_83 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_84 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_85 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_86 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_87 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_88 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_89 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_90 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_91 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_92 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_93 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_94 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_95 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_96 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_97 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_98 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_99 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_100 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_101 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_102 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_103 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_104 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_105 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_106 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_107 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_108 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_109 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_110 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_111 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_112 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_113 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_114 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_115 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_116 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_117 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_118 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_119 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_120 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_121 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_122 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_123 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_124 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_125 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_126 <= 2'b01; // @ Data.scala l409
      GSHARE_PHT_127 <= 2'b01; // @ Data.scala l409
      BTB_valid <= 4'b0000; // @ Data.scala l409
      BTB_source_pc_0 <= 32'h00000000; // @ Data.scala l409
      BTB_source_pc_1 <= 32'h00000000; // @ Data.scala l409
      BTB_source_pc_2 <= 32'h00000000; // @ Data.scala l409
      BTB_source_pc_3 <= 32'h00000000; // @ Data.scala l409
      BTB_call <= 4'b0000; // @ Data.scala l409
      BTB_ret <= 4'b0000; // @ Data.scala l409
      BTB_jump <= 4'b0000; // @ Data.scala l409
      BTB_target_pc_0 <= 32'h00000000; // @ Data.scala l409
      BTB_target_pc_1 <= 32'h00000000; // @ Data.scala l409
      BTB_target_pc_2 <= 32'h00000000; // @ Data.scala l409
      BTB_target_pc_3 <= 32'h00000000; // @ Data.scala l409
      BTB_btb_alloc_index_value <= 2'b00; // @ Data.scala l409
      RAS_ras_curr_index <= 2'b00; // @ Data.scala l409
      RAS_ras_curr_index_proven <= 2'b00; // @ Data.scala l409
    end else begin
      if(train_valid) begin
        if(tmp_1[0]) begin
          GSHARE_PHT_0 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[1]) begin
          GSHARE_PHT_1 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[2]) begin
          GSHARE_PHT_2 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[3]) begin
          GSHARE_PHT_3 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[4]) begin
          GSHARE_PHT_4 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[5]) begin
          GSHARE_PHT_5 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[6]) begin
          GSHARE_PHT_6 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[7]) begin
          GSHARE_PHT_7 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[8]) begin
          GSHARE_PHT_8 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[9]) begin
          GSHARE_PHT_9 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[10]) begin
          GSHARE_PHT_10 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[11]) begin
          GSHARE_PHT_11 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[12]) begin
          GSHARE_PHT_12 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[13]) begin
          GSHARE_PHT_13 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[14]) begin
          GSHARE_PHT_14 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[15]) begin
          GSHARE_PHT_15 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[16]) begin
          GSHARE_PHT_16 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[17]) begin
          GSHARE_PHT_17 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[18]) begin
          GSHARE_PHT_18 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[19]) begin
          GSHARE_PHT_19 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[20]) begin
          GSHARE_PHT_20 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[21]) begin
          GSHARE_PHT_21 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[22]) begin
          GSHARE_PHT_22 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[23]) begin
          GSHARE_PHT_23 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[24]) begin
          GSHARE_PHT_24 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[25]) begin
          GSHARE_PHT_25 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[26]) begin
          GSHARE_PHT_26 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[27]) begin
          GSHARE_PHT_27 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[28]) begin
          GSHARE_PHT_28 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[29]) begin
          GSHARE_PHT_29 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[30]) begin
          GSHARE_PHT_30 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[31]) begin
          GSHARE_PHT_31 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[32]) begin
          GSHARE_PHT_32 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[33]) begin
          GSHARE_PHT_33 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[34]) begin
          GSHARE_PHT_34 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[35]) begin
          GSHARE_PHT_35 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[36]) begin
          GSHARE_PHT_36 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[37]) begin
          GSHARE_PHT_37 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[38]) begin
          GSHARE_PHT_38 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[39]) begin
          GSHARE_PHT_39 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[40]) begin
          GSHARE_PHT_40 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[41]) begin
          GSHARE_PHT_41 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[42]) begin
          GSHARE_PHT_42 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[43]) begin
          GSHARE_PHT_43 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[44]) begin
          GSHARE_PHT_44 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[45]) begin
          GSHARE_PHT_45 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[46]) begin
          GSHARE_PHT_46 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[47]) begin
          GSHARE_PHT_47 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[48]) begin
          GSHARE_PHT_48 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[49]) begin
          GSHARE_PHT_49 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[50]) begin
          GSHARE_PHT_50 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[51]) begin
          GSHARE_PHT_51 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[52]) begin
          GSHARE_PHT_52 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[53]) begin
          GSHARE_PHT_53 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[54]) begin
          GSHARE_PHT_54 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[55]) begin
          GSHARE_PHT_55 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[56]) begin
          GSHARE_PHT_56 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[57]) begin
          GSHARE_PHT_57 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[58]) begin
          GSHARE_PHT_58 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[59]) begin
          GSHARE_PHT_59 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[60]) begin
          GSHARE_PHT_60 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[61]) begin
          GSHARE_PHT_61 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[62]) begin
          GSHARE_PHT_62 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[63]) begin
          GSHARE_PHT_63 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[64]) begin
          GSHARE_PHT_64 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[65]) begin
          GSHARE_PHT_65 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[66]) begin
          GSHARE_PHT_66 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[67]) begin
          GSHARE_PHT_67 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[68]) begin
          GSHARE_PHT_68 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[69]) begin
          GSHARE_PHT_69 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[70]) begin
          GSHARE_PHT_70 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[71]) begin
          GSHARE_PHT_71 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[72]) begin
          GSHARE_PHT_72 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[73]) begin
          GSHARE_PHT_73 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[74]) begin
          GSHARE_PHT_74 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[75]) begin
          GSHARE_PHT_75 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[76]) begin
          GSHARE_PHT_76 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[77]) begin
          GSHARE_PHT_77 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[78]) begin
          GSHARE_PHT_78 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[79]) begin
          GSHARE_PHT_79 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[80]) begin
          GSHARE_PHT_80 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[81]) begin
          GSHARE_PHT_81 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[82]) begin
          GSHARE_PHT_82 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[83]) begin
          GSHARE_PHT_83 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[84]) begin
          GSHARE_PHT_84 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[85]) begin
          GSHARE_PHT_85 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[86]) begin
          GSHARE_PHT_86 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[87]) begin
          GSHARE_PHT_87 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[88]) begin
          GSHARE_PHT_88 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[89]) begin
          GSHARE_PHT_89 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[90]) begin
          GSHARE_PHT_90 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[91]) begin
          GSHARE_PHT_91 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[92]) begin
          GSHARE_PHT_92 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[93]) begin
          GSHARE_PHT_93 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[94]) begin
          GSHARE_PHT_94 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[95]) begin
          GSHARE_PHT_95 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[96]) begin
          GSHARE_PHT_96 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[97]) begin
          GSHARE_PHT_97 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[98]) begin
          GSHARE_PHT_98 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[99]) begin
          GSHARE_PHT_99 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[100]) begin
          GSHARE_PHT_100 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[101]) begin
          GSHARE_PHT_101 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[102]) begin
          GSHARE_PHT_102 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[103]) begin
          GSHARE_PHT_103 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[104]) begin
          GSHARE_PHT_104 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[105]) begin
          GSHARE_PHT_105 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[106]) begin
          GSHARE_PHT_106 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[107]) begin
          GSHARE_PHT_107 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[108]) begin
          GSHARE_PHT_108 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[109]) begin
          GSHARE_PHT_109 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[110]) begin
          GSHARE_PHT_110 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[111]) begin
          GSHARE_PHT_111 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[112]) begin
          GSHARE_PHT_112 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[113]) begin
          GSHARE_PHT_113 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[114]) begin
          GSHARE_PHT_114 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[115]) begin
          GSHARE_PHT_115 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[116]) begin
          GSHARE_PHT_116 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[117]) begin
          GSHARE_PHT_117 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[118]) begin
          GSHARE_PHT_118 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[119]) begin
          GSHARE_PHT_119 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[120]) begin
          GSHARE_PHT_120 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[121]) begin
          GSHARE_PHT_121 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[122]) begin
          GSHARE_PHT_122 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[123]) begin
          GSHARE_PHT_123 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[124]) begin
          GSHARE_PHT_124 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[125]) begin
          GSHARE_PHT_125 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[126]) begin
          GSHARE_PHT_126 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
        if(tmp_1[127]) begin
          GSHARE_PHT_127 <= tmp_GSHARE_PHT_0; // @ Predictor.scala l43
        end
      end
      if((train_valid && train_mispredicted)) begin
        GSHARE_global_history_reg <= {GSHARE_global_history_reg[5 : 0],train_taken}; // @ Predictor.scala l52
      end else begin
        if(predict_taken) begin
          GSHARE_global_history_reg <= {GSHARE_global_history_reg[5 : 0],predict_taken}; // @ Predictor.scala l54
        end
      end
      BTB_btb_alloc_index_value <= BTB_btb_alloc_index_valueNext; // @ Reg.scala l39
      if(BTB_btb_is_hit) begin
        if(tmp_2[0]) begin
          BTB_source_pc_0 <= train_pc; // @ Predictor.scala l111
        end
        if(tmp_2[1]) begin
          BTB_source_pc_1 <= train_pc; // @ Predictor.scala l111
        end
        if(tmp_2[2]) begin
          BTB_source_pc_2 <= train_pc; // @ Predictor.scala l111
        end
        if(tmp_2[3]) begin
          BTB_source_pc_3 <= train_pc; // @ Predictor.scala l111
        end
        BTB_call[BTB_btb_write_index] <= train_is_call; // @ Predictor.scala l112
        BTB_ret[BTB_btb_write_index] <= train_is_return; // @ Predictor.scala l113
        BTB_jump[BTB_btb_write_index] <= train_is_jump; // @ Predictor.scala l114
        if(tmp_3[0]) begin
          BTB_target_pc_0 <= train_pc_next; // @ Predictor.scala l115
        end
        if(tmp_3[1]) begin
          BTB_target_pc_1 <= train_pc_next; // @ Predictor.scala l115
        end
        if(tmp_3[2]) begin
          BTB_target_pc_2 <= train_pc_next; // @ Predictor.scala l115
        end
        if(tmp_3[3]) begin
          BTB_target_pc_3 <= train_pc_next; // @ Predictor.scala l115
        end
      end else begin
        if(BTB_btb_is_miss) begin
          BTB_valid[BTB_btb_alloc_index_value] <= 1'b1; // @ Predictor.scala l117
          if(tmp_4[0]) begin
            BTB_source_pc_0 <= train_pc; // @ Predictor.scala l118
          end
          if(tmp_4[1]) begin
            BTB_source_pc_1 <= train_pc; // @ Predictor.scala l118
          end
          if(tmp_4[2]) begin
            BTB_source_pc_2 <= train_pc; // @ Predictor.scala l118
          end
          if(tmp_4[3]) begin
            BTB_source_pc_3 <= train_pc; // @ Predictor.scala l118
          end
          BTB_call[BTB_btb_write_index] <= train_is_call; // @ Predictor.scala l119
          BTB_ret[BTB_btb_write_index] <= train_is_return; // @ Predictor.scala l120
          BTB_jump[BTB_btb_write_index] <= train_is_jump; // @ Predictor.scala l121
          if(tmp_5[0]) begin
            BTB_target_pc_0 <= train_pc_next; // @ Predictor.scala l122
          end
          if(tmp_5[1]) begin
            BTB_target_pc_1 <= train_pc_next; // @ Predictor.scala l122
          end
          if(tmp_5[2]) begin
            BTB_target_pc_2 <= train_pc_next; // @ Predictor.scala l122
          end
          if(tmp_5[3]) begin
            BTB_target_pc_3 <= train_pc_next; // @ Predictor.scala l122
          end
        end
      end
      RAS_ras_curr_index_proven <= RAS_ras_next_index; // @ Reg.scala l39
      if(tmp_when_8) begin
        RAS_ras_curr_index <= RAS_ras_next_index; // @ Predictor.scala l162
      end else begin
        if(RAS_ras_call_matched) begin
          RAS_ras_curr_index <= RAS_ras_next_index; // @ Predictor.scala l165
        end else begin
          if(((train_mispredicted && train_valid) && train_is_return)) begin
            RAS_ras_curr_index <= RAS_ras_next_index; // @ Predictor.scala l167
          end else begin
            if(RAS_ras_ret_matched) begin
              RAS_ras_curr_index <= RAS_ras_next_index; // @ Predictor.scala l169
            end
          end
        end
      end
    end
  end

  always @(posedge clk) begin
    if(tmp_when_8) begin
      if(tmp_7) begin
        RAS_ras_regfile_0 <= tmp_RAS_ras_regfile_0; // @ Predictor.scala l161
      end
      if(tmp_8) begin
        RAS_ras_regfile_1 <= tmp_RAS_ras_regfile_0; // @ Predictor.scala l161
      end
      if(tmp_9) begin
        RAS_ras_regfile_2 <= tmp_RAS_ras_regfile_0; // @ Predictor.scala l161
      end
      if(tmp_10) begin
        RAS_ras_regfile_3 <= tmp_RAS_ras_regfile_0; // @ Predictor.scala l161
      end
    end else begin
      if(RAS_ras_call_matched) begin
        if(tmp_7) begin
          RAS_ras_regfile_0 <= tmp_RAS_ras_regfile_0_1; // @ Predictor.scala l164
        end
        if(tmp_8) begin
          RAS_ras_regfile_1 <= tmp_RAS_ras_regfile_0_1; // @ Predictor.scala l164
        end
        if(tmp_9) begin
          RAS_ras_regfile_2 <= tmp_RAS_ras_regfile_0_1; // @ Predictor.scala l164
        end
        if(tmp_10) begin
          RAS_ras_regfile_3 <= tmp_RAS_ras_regfile_0_1; // @ Predictor.scala l164
        end
      end
    end
  end


endmodule

module RegFileModule (
  output wire [31:0]   read_ports_rs1_value,
  output wire [31:0]   read_ports_rs2_value,
  input  wire [4:0]    read_ports_rs1_addr,
  input  wire [4:0]    read_ports_rs2_addr,
  input  wire          read_ports_rs1_req,
  input  wire          read_ports_rs2_req,
  input  wire [31:0]   write_ports_rd_value,
  input  wire [4:0]    write_ports_rd_addr,
  input  wire          write_ports_rd_wen,
  input  wire          clk,
  input  wire          reset
);

  reg        [31:0]   tmp_read_value_1;
  reg        [31:0]   tmp_read_value_2;
  reg        [31:0]   reg_file_0;
  reg        [31:0]   reg_file_1;
  reg        [31:0]   reg_file_2;
  reg        [31:0]   reg_file_3;
  reg        [31:0]   reg_file_4;
  reg        [31:0]   reg_file_5;
  reg        [31:0]   reg_file_6;
  reg        [31:0]   reg_file_7;
  reg        [31:0]   reg_file_8;
  reg        [31:0]   reg_file_9;
  reg        [31:0]   reg_file_10;
  reg        [31:0]   reg_file_11;
  reg        [31:0]   reg_file_12;
  reg        [31:0]   reg_file_13;
  reg        [31:0]   reg_file_14;
  reg        [31:0]   reg_file_15;
  reg        [31:0]   reg_file_16;
  reg        [31:0]   reg_file_17;
  reg        [31:0]   reg_file_18;
  reg        [31:0]   reg_file_19;
  reg        [31:0]   reg_file_20;
  reg        [31:0]   reg_file_21;
  reg        [31:0]   reg_file_22;
  reg        [31:0]   reg_file_23;
  reg        [31:0]   reg_file_24;
  reg        [31:0]   reg_file_25;
  reg        [31:0]   reg_file_26;
  reg        [31:0]   reg_file_27;
  reg        [31:0]   reg_file_28;
  reg        [31:0]   reg_file_29;
  reg        [31:0]   reg_file_30;
  reg        [31:0]   reg_file_31;
  wire       [31:0]   read_value_1;
  wire       [31:0]   read_value_2;
  wire       [31:0]   tmp_1;

  always @(*) begin
    case(read_ports_rs1_addr)
      5'b00000 : tmp_read_value_1 = reg_file_0;
      5'b00001 : tmp_read_value_1 = reg_file_1;
      5'b00010 : tmp_read_value_1 = reg_file_2;
      5'b00011 : tmp_read_value_1 = reg_file_3;
      5'b00100 : tmp_read_value_1 = reg_file_4;
      5'b00101 : tmp_read_value_1 = reg_file_5;
      5'b00110 : tmp_read_value_1 = reg_file_6;
      5'b00111 : tmp_read_value_1 = reg_file_7;
      5'b01000 : tmp_read_value_1 = reg_file_8;
      5'b01001 : tmp_read_value_1 = reg_file_9;
      5'b01010 : tmp_read_value_1 = reg_file_10;
      5'b01011 : tmp_read_value_1 = reg_file_11;
      5'b01100 : tmp_read_value_1 = reg_file_12;
      5'b01101 : tmp_read_value_1 = reg_file_13;
      5'b01110 : tmp_read_value_1 = reg_file_14;
      5'b01111 : tmp_read_value_1 = reg_file_15;
      5'b10000 : tmp_read_value_1 = reg_file_16;
      5'b10001 : tmp_read_value_1 = reg_file_17;
      5'b10010 : tmp_read_value_1 = reg_file_18;
      5'b10011 : tmp_read_value_1 = reg_file_19;
      5'b10100 : tmp_read_value_1 = reg_file_20;
      5'b10101 : tmp_read_value_1 = reg_file_21;
      5'b10110 : tmp_read_value_1 = reg_file_22;
      5'b10111 : tmp_read_value_1 = reg_file_23;
      5'b11000 : tmp_read_value_1 = reg_file_24;
      5'b11001 : tmp_read_value_1 = reg_file_25;
      5'b11010 : tmp_read_value_1 = reg_file_26;
      5'b11011 : tmp_read_value_1 = reg_file_27;
      5'b11100 : tmp_read_value_1 = reg_file_28;
      5'b11101 : tmp_read_value_1 = reg_file_29;
      5'b11110 : tmp_read_value_1 = reg_file_30;
      default : tmp_read_value_1 = reg_file_31;
    endcase
  end

  always @(*) begin
    case(read_ports_rs2_addr)
      5'b00000 : tmp_read_value_2 = reg_file_0;
      5'b00001 : tmp_read_value_2 = reg_file_1;
      5'b00010 : tmp_read_value_2 = reg_file_2;
      5'b00011 : tmp_read_value_2 = reg_file_3;
      5'b00100 : tmp_read_value_2 = reg_file_4;
      5'b00101 : tmp_read_value_2 = reg_file_5;
      5'b00110 : tmp_read_value_2 = reg_file_6;
      5'b00111 : tmp_read_value_2 = reg_file_7;
      5'b01000 : tmp_read_value_2 = reg_file_8;
      5'b01001 : tmp_read_value_2 = reg_file_9;
      5'b01010 : tmp_read_value_2 = reg_file_10;
      5'b01011 : tmp_read_value_2 = reg_file_11;
      5'b01100 : tmp_read_value_2 = reg_file_12;
      5'b01101 : tmp_read_value_2 = reg_file_13;
      5'b01110 : tmp_read_value_2 = reg_file_14;
      5'b01111 : tmp_read_value_2 = reg_file_15;
      5'b10000 : tmp_read_value_2 = reg_file_16;
      5'b10001 : tmp_read_value_2 = reg_file_17;
      5'b10010 : tmp_read_value_2 = reg_file_18;
      5'b10011 : tmp_read_value_2 = reg_file_19;
      5'b10100 : tmp_read_value_2 = reg_file_20;
      5'b10101 : tmp_read_value_2 = reg_file_21;
      5'b10110 : tmp_read_value_2 = reg_file_22;
      5'b10111 : tmp_read_value_2 = reg_file_23;
      5'b11000 : tmp_read_value_2 = reg_file_24;
      5'b11001 : tmp_read_value_2 = reg_file_25;
      5'b11010 : tmp_read_value_2 = reg_file_26;
      5'b11011 : tmp_read_value_2 = reg_file_27;
      5'b11100 : tmp_read_value_2 = reg_file_28;
      5'b11101 : tmp_read_value_2 = reg_file_29;
      5'b11110 : tmp_read_value_2 = reg_file_30;
      default : tmp_read_value_2 = reg_file_31;
    endcase
  end

  assign read_value_1 = tmp_read_value_1; // @ Vec.scala l202
  assign read_value_2 = tmp_read_value_2; // @ Vec.scala l202
  assign tmp_1 = ({31'd0,1'b1} <<< write_ports_rd_addr); // @ BaseType.scala l299
  assign read_ports_rs1_value = (((write_ports_rd_wen && ((write_ports_rd_addr == read_ports_rs1_addr) && (write_ports_rd_addr != 5'h00))) && read_ports_rs1_req) ? write_ports_rd_value : read_value_1); // @ DecodePlugin.scala l47
  assign read_ports_rs2_value = (((write_ports_rd_wen && ((write_ports_rd_addr == read_ports_rs2_addr) && (write_ports_rd_addr != 5'h00))) && read_ports_rs2_req) ? write_ports_rd_value : read_value_2); // @ DecodePlugin.scala l49
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      reg_file_0 <= 32'h00000000; // @ Data.scala l409
      reg_file_1 <= 32'h00000000; // @ Data.scala l409
      reg_file_2 <= 32'h00000000; // @ Data.scala l409
      reg_file_3 <= 32'h00000000; // @ Data.scala l409
      reg_file_4 <= 32'h00000000; // @ Data.scala l409
      reg_file_5 <= 32'h00000000; // @ Data.scala l409
      reg_file_6 <= 32'h00000000; // @ Data.scala l409
      reg_file_7 <= 32'h00000000; // @ Data.scala l409
      reg_file_8 <= 32'h00000000; // @ Data.scala l409
      reg_file_9 <= 32'h00000000; // @ Data.scala l409
      reg_file_10 <= 32'h00000000; // @ Data.scala l409
      reg_file_11 <= 32'h00000000; // @ Data.scala l409
      reg_file_12 <= 32'h00000000; // @ Data.scala l409
      reg_file_13 <= 32'h00000000; // @ Data.scala l409
      reg_file_14 <= 32'h00000000; // @ Data.scala l409
      reg_file_15 <= 32'h00000000; // @ Data.scala l409
      reg_file_16 <= 32'h00000000; // @ Data.scala l409
      reg_file_17 <= 32'h00000000; // @ Data.scala l409
      reg_file_18 <= 32'h00000000; // @ Data.scala l409
      reg_file_19 <= 32'h00000000; // @ Data.scala l409
      reg_file_20 <= 32'h00000000; // @ Data.scala l409
      reg_file_21 <= 32'h00000000; // @ Data.scala l409
      reg_file_22 <= 32'h00000000; // @ Data.scala l409
      reg_file_23 <= 32'h00000000; // @ Data.scala l409
      reg_file_24 <= 32'h00000000; // @ Data.scala l409
      reg_file_25 <= 32'h00000000; // @ Data.scala l409
      reg_file_26 <= 32'h00000000; // @ Data.scala l409
      reg_file_27 <= 32'h00000000; // @ Data.scala l409
      reg_file_28 <= 32'h00000000; // @ Data.scala l409
      reg_file_29 <= 32'h00000000; // @ Data.scala l409
      reg_file_30 <= 32'h00000000; // @ Data.scala l409
      reg_file_31 <= 32'h00000000; // @ Data.scala l409
    end else begin
      if((write_ports_rd_wen && (write_ports_rd_addr != 5'h00))) begin
        if(tmp_1[0]) begin
          reg_file_0 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[1]) begin
          reg_file_1 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[2]) begin
          reg_file_2 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[3]) begin
          reg_file_3 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[4]) begin
          reg_file_4 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[5]) begin
          reg_file_5 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[6]) begin
          reg_file_6 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[7]) begin
          reg_file_7 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[8]) begin
          reg_file_8 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[9]) begin
          reg_file_9 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[10]) begin
          reg_file_10 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[11]) begin
          reg_file_11 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[12]) begin
          reg_file_12 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[13]) begin
          reg_file_13 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[14]) begin
          reg_file_14 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[15]) begin
          reg_file_15 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[16]) begin
          reg_file_16 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[17]) begin
          reg_file_17 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[18]) begin
          reg_file_18 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[19]) begin
          reg_file_19 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[20]) begin
          reg_file_20 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[21]) begin
          reg_file_21 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[22]) begin
          reg_file_22 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[23]) begin
          reg_file_23 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[24]) begin
          reg_file_24 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[25]) begin
          reg_file_25 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[26]) begin
          reg_file_26 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[27]) begin
          reg_file_27 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[28]) begin
          reg_file_28 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[29]) begin
          reg_file_29 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[30]) begin
          reg_file_30 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
        if(tmp_1[31]) begin
          reg_file_31 <= write_ports_rd_value; // @ DecodePlugin.scala l44
        end
      end
    end
  end


endmodule

module FIFO_2 (
  input  wire          ports_s_ports_valid,
  output wire          ports_s_ports_ready,
  input  wire [31:0]   ports_s_ports_payload,
  output wire          ports_m_ports_valid,
  input  wire          ports_m_ports_ready,
  output wire [31:0]   ports_m_ports_payload,
  input  wire          flush,
  input  wire          clk,
  input  wire          reset
);

  reg        [31:0]   tmp_ports_m_ports_payload;
  reg        [2:0]    read_ptr;
  reg        [2:0]    write_ptr;
  wire       [1:0]    read_addr;
  wire       [1:0]    next_read_addr;
  wire       [1:0]    write_addr;
  wire                fifo_empty;
  wire                fifo_full;
  reg        [31:0]   fifo_ram_0;
  reg        [31:0]   fifo_ram_1;
  reg        [31:0]   fifo_ram_2;
  reg        [31:0]   fifo_ram_3;
  wire                ports_m_ports_fire;
  wire       [3:0]    tmp_1;
  wire                ports_s_ports_fire;

  always @(*) begin
    case(read_addr)
      2'b00 : tmp_ports_m_ports_payload = fifo_ram_0;
      2'b01 : tmp_ports_m_ports_payload = fifo_ram_1;
      2'b10 : tmp_ports_m_ports_payload = fifo_ram_2;
      default : tmp_ports_m_ports_payload = fifo_ram_3;
    endcase
  end

  assign read_addr = read_ptr[1 : 0]; // @ BaseType.scala l299
  assign next_read_addr = (read_addr + 2'b01); // @ BaseType.scala l299
  assign write_addr = write_ptr[1 : 0]; // @ BaseType.scala l299
  assign fifo_empty = (read_ptr == write_ptr); // @ BaseType.scala l305
  assign fifo_full = ((read_addr == write_addr) && (read_ptr[2] != write_ptr[2])); // @ BaseType.scala l305
  assign ports_m_ports_fire = (ports_m_ports_valid && ports_m_ports_ready); // @ BaseType.scala l305
  assign tmp_1 = ({3'd0,1'b1} <<< write_addr); // @ BaseType.scala l299
  assign ports_s_ports_fire = (ports_s_ports_valid && ports_s_ports_ready); // @ BaseType.scala l305
  assign ports_s_ports_ready = (! fifo_full); // @ FIFO.scala l43
  assign ports_m_ports_valid = (! fifo_empty); // @ FIFO.scala l44
  assign ports_m_ports_payload = tmp_ports_m_ports_payload; // @ FIFO.scala l45
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      read_ptr <= 3'b000; // @ Data.scala l409
      write_ptr <= 3'b000; // @ Data.scala l409
    end else begin
      if(flush) begin
        read_ptr <= 3'b000; // @ FIFO.scala l31
      end else begin
        if(ports_m_ports_fire) begin
          read_ptr <= (read_ptr + 3'b001); // @ FIFO.scala l33
        end
      end
      if(flush) begin
        write_ptr <= 3'b000; // @ FIFO.scala l37
      end else begin
        if(ports_s_ports_fire) begin
          write_ptr <= (write_ptr + 3'b001); // @ FIFO.scala l39
        end
      end
    end
  end

  always @(posedge clk) begin
    if(!flush) begin
      if(ports_s_ports_fire) begin
        if(tmp_1[0]) begin
          fifo_ram_0 <= ports_s_ports_payload; // @ FIFO.scala l40
        end
        if(tmp_1[1]) begin
          fifo_ram_1 <= ports_s_ports_payload; // @ FIFO.scala l40
        end
        if(tmp_1[2]) begin
          fifo_ram_2 <= ports_s_ports_payload; // @ FIFO.scala l40
        end
        if(tmp_1[3]) begin
          fifo_ram_3 <= ports_s_ports_payload; // @ FIFO.scala l40
        end
      end
    end
  end


endmodule

module FIFO_1 (
  input  wire          ports_s_ports_valid,
  output wire          ports_s_ports_ready,
  input  wire          ports_s_ports_payload,
  output wire          ports_m_ports_valid,
  input  wire          ports_m_ports_ready,
  output wire          ports_m_ports_payload,
  input  wire          flush,
  input  wire          clk,
  input  wire          reset
);

  reg                 tmp_ports_m_ports_payload;
  reg        [2:0]    read_ptr;
  reg        [2:0]    write_ptr;
  wire       [1:0]    read_addr;
  wire       [1:0]    next_read_addr;
  wire       [1:0]    write_addr;
  wire                fifo_empty;
  wire                fifo_full;
  reg                 fifo_ram_0;
  reg                 fifo_ram_1;
  reg                 fifo_ram_2;
  reg                 fifo_ram_3;
  wire                ports_m_ports_fire;
  wire       [3:0]    tmp_1;
  wire                ports_s_ports_fire;

  always @(*) begin
    case(read_addr)
      2'b00 : tmp_ports_m_ports_payload = fifo_ram_0;
      2'b01 : tmp_ports_m_ports_payload = fifo_ram_1;
      2'b10 : tmp_ports_m_ports_payload = fifo_ram_2;
      default : tmp_ports_m_ports_payload = fifo_ram_3;
    endcase
  end

  assign read_addr = read_ptr[1 : 0]; // @ BaseType.scala l299
  assign next_read_addr = (read_addr + 2'b01); // @ BaseType.scala l299
  assign write_addr = write_ptr[1 : 0]; // @ BaseType.scala l299
  assign fifo_empty = (read_ptr == write_ptr); // @ BaseType.scala l305
  assign fifo_full = ((read_addr == write_addr) && (read_ptr[2] != write_ptr[2])); // @ BaseType.scala l305
  assign ports_m_ports_fire = (ports_m_ports_valid && ports_m_ports_ready); // @ BaseType.scala l305
  assign tmp_1 = ({3'd0,1'b1} <<< write_addr); // @ BaseType.scala l299
  assign ports_s_ports_fire = (ports_s_ports_valid && ports_s_ports_ready); // @ BaseType.scala l305
  assign ports_s_ports_ready = (! fifo_full); // @ FIFO.scala l43
  assign ports_m_ports_valid = (! fifo_empty); // @ FIFO.scala l44
  assign ports_m_ports_payload = tmp_ports_m_ports_payload; // @ FIFO.scala l45
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      read_ptr <= 3'b000; // @ Data.scala l409
      write_ptr <= 3'b000; // @ Data.scala l409
    end else begin
      if(flush) begin
        read_ptr <= 3'b000; // @ FIFO.scala l31
      end else begin
        if(ports_m_ports_fire) begin
          read_ptr <= (read_ptr + 3'b001); // @ FIFO.scala l33
        end
      end
      if(flush) begin
        write_ptr <= 3'b000; // @ FIFO.scala l37
      end else begin
        if(ports_s_ports_fire) begin
          write_ptr <= (write_ptr + 3'b001); // @ FIFO.scala l39
        end
      end
    end
  end

  always @(posedge clk) begin
    if(!flush) begin
      if(ports_s_ports_fire) begin
        if(tmp_1[0]) begin
          fifo_ram_0 <= ports_s_ports_payload; // @ FIFO.scala l40
        end
        if(tmp_1[1]) begin
          fifo_ram_1 <= ports_s_ports_payload; // @ FIFO.scala l40
        end
        if(tmp_1[2]) begin
          fifo_ram_2 <= ports_s_ports_payload; // @ FIFO.scala l40
        end
        if(tmp_1[3]) begin
          fifo_ram_3 <= ports_s_ports_payload; // @ FIFO.scala l40
        end
      end
    end
  end


endmodule

module FIFO (
  input  wire          ports_s_ports_valid,
  output wire          ports_s_ports_ready,
  input  wire [31:0]   ports_s_ports_payload,
  output wire          ports_m_ports_valid,
  input  wire          ports_m_ports_ready,
  output wire [31:0]   ports_m_ports_payload,
  input  wire          flush,
  output wire [31:0]   next_payload,
  output wire          next_valid,
  input  wire          clk,
  input  wire          reset
);

  reg        [31:0]   tmp_ports_m_ports_payload;
  reg        [31:0]   tmp_next_payload;
  reg        [2:0]    read_ptr;
  reg        [2:0]    write_ptr;
  wire       [1:0]    read_addr;
  wire       [1:0]    next_read_addr;
  wire       [1:0]    write_addr;
  wire                fifo_empty;
  wire                fifo_full;
  reg        [31:0]   fifo_ram_0;
  reg        [31:0]   fifo_ram_1;
  reg        [31:0]   fifo_ram_2;
  reg        [31:0]   fifo_ram_3;
  wire                ports_m_ports_fire;
  wire       [3:0]    tmp_1;
  wire                ports_s_ports_fire;
  reg        [2:0]    fifo_cnt;

  always @(*) begin
    case(read_addr)
      2'b00 : tmp_ports_m_ports_payload = fifo_ram_0;
      2'b01 : tmp_ports_m_ports_payload = fifo_ram_1;
      2'b10 : tmp_ports_m_ports_payload = fifo_ram_2;
      default : tmp_ports_m_ports_payload = fifo_ram_3;
    endcase
  end

  always @(*) begin
    case(next_read_addr)
      2'b00 : tmp_next_payload = fifo_ram_0;
      2'b01 : tmp_next_payload = fifo_ram_1;
      2'b10 : tmp_next_payload = fifo_ram_2;
      default : tmp_next_payload = fifo_ram_3;
    endcase
  end

  assign read_addr = read_ptr[1 : 0]; // @ BaseType.scala l299
  assign next_read_addr = (read_addr + 2'b01); // @ BaseType.scala l299
  assign write_addr = write_ptr[1 : 0]; // @ BaseType.scala l299
  assign fifo_empty = (read_ptr == write_ptr); // @ BaseType.scala l305
  assign fifo_full = ((read_addr == write_addr) && (read_ptr[2] != write_ptr[2])); // @ BaseType.scala l305
  assign ports_m_ports_fire = (ports_m_ports_valid && ports_m_ports_ready); // @ BaseType.scala l305
  assign tmp_1 = ({3'd0,1'b1} <<< write_addr); // @ BaseType.scala l299
  assign ports_s_ports_fire = (ports_s_ports_valid && ports_s_ports_ready); // @ BaseType.scala l305
  assign ports_s_ports_ready = (! fifo_full); // @ FIFO.scala l43
  assign ports_m_ports_valid = (! fifo_empty); // @ FIFO.scala l44
  assign ports_m_ports_payload = tmp_ports_m_ports_payload; // @ FIFO.scala l45
  assign next_payload = tmp_next_payload; // @ FIFO.scala l51
  assign next_valid = (3'b010 <= fifo_cnt); // @ FIFO.scala l61
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      read_ptr <= 3'b000; // @ Data.scala l409
      write_ptr <= 3'b000; // @ Data.scala l409
      fifo_cnt <= 3'b000; // @ Data.scala l409
    end else begin
      if(flush) begin
        read_ptr <= 3'b000; // @ FIFO.scala l31
      end else begin
        if(ports_m_ports_fire) begin
          read_ptr <= (read_ptr + 3'b001); // @ FIFO.scala l33
        end
      end
      if(flush) begin
        write_ptr <= 3'b000; // @ FIFO.scala l37
      end else begin
        if(ports_s_ports_fire) begin
          write_ptr <= (write_ptr + 3'b001); // @ FIFO.scala l39
        end
      end
      if(flush) begin
        fifo_cnt <= 3'b000; // @ FIFO.scala l53
      end else begin
        if((ports_s_ports_fire && (! ports_m_ports_fire))) begin
          fifo_cnt <= (fifo_cnt + 3'b001); // @ FIFO.scala l55
        end else begin
          if(((! ports_s_ports_fire) && ports_m_ports_fire)) begin
            fifo_cnt <= (fifo_cnt - 3'b001); // @ FIFO.scala l57
          end
        end
      end
    end
  end

  always @(posedge clk) begin
    if(!flush) begin
      if(ports_s_ports_fire) begin
        if(tmp_1[0]) begin
          fifo_ram_0 <= ports_s_ports_payload; // @ FIFO.scala l40
        end
        if(tmp_1[1]) begin
          fifo_ram_1 <= ports_s_ports_payload; // @ FIFO.scala l40
        end
        if(tmp_1[2]) begin
          fifo_ram_2 <= ports_s_ports_payload; // @ FIFO.scala l40
        end
        if(tmp_1[3]) begin
          fifo_ram_3 <= ports_s_ports_payload; // @ FIFO.scala l40
        end
      end
    end
  end


endmodule
